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System Control Block (SCB)
Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC)

Type definitions for the System Control Block Registers. More...

Topics

 System Controls not in SCB (SCnSCB)
 Type definitions for the System Control and ID Register not in the SCB.
 
 Implementation Control Block register (ICB)
 Type definitions for the Implementation Control Block Register.
 

Classes

struct  SCB_Type
 Structure type to access the System Control Block (SCB). More...
 
struct  EMSS_Type
 

Macros

#define TPI_ACPR_SWOSCALER_Pos   0U
 
#define TPI_ACPR_SWOSCALER_Msk   (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)
 
#define TPI_PSCR_PSCount_Pos   0U
 
#define TPI_PSCR_PSCount_Msk   (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)
 
#define TPI_LSR_nTT_Pos   1U
 
#define TPI_LSR_nTT_Msk   (0x1UL << TPI_LSR_nTT_Pos)
 
#define TPI_LSR_SLK_Pos   1U
 
#define TPI_LSR_SLK_Msk   (0x1UL << TPI_LSR_SLK_Pos)
 
#define TPI_LSR_SLI_Pos   0U
 
#define TPI_LSR_SLI_Msk   (0x1UL /*<< TPI_LSR_SLI_Pos*/)
 
#define TPI_ACPR_SWOSCALER_Pos   0U
 
#define TPI_ACPR_SWOSCALER_Msk   (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)
 
#define TPI_PSCR_PSCount_Pos   0U
 
#define TPI_PSCR_PSCount_Msk   (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)
 
#define TPI_LSR_nTT_Pos   1U
 
#define TPI_LSR_nTT_Msk   (0x1UL << TPI_LSR_nTT_Pos)
 
#define TPI_LSR_SLK_Pos   1U
 
#define TPI_LSR_SLK_Msk   (0x1UL << TPI_LSR_SLK_Pos)
 
#define TPI_LSR_SLI_Pos   0U
 
#define TPI_LSR_SLI_Msk   (0x1UL /*<< TPI_LSR_SLI_Pos*/)
 
#define TPI_ACPR_SWOSCALER_Pos   0U
 
#define TPI_ACPR_SWOSCALER_Msk   (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)
 
#define TPI_FFCR_EnFmt_Pos   0U
 
#define TPI_FFCR_EnFmt_Msk   (0x3UL << /*TPI_FFCR_EnFmt_Pos*/)
 
#define TPI_PSCR_PSCount_Pos   0U
 
#define TPI_PSCR_PSCount_Msk   (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)
 
#define TPI_LSR_nTT_Pos   1U
 
#define TPI_LSR_nTT_Msk   (0x1UL << TPI_LSR_nTT_Pos)
 
#define TPI_LSR_SLK_Pos   1U
 
#define TPI_LSR_SLK_Msk   (0x1UL << TPI_LSR_SLK_Pos)
 
#define TPI_LSR_SLI_Pos   0U
 
#define TPI_LSR_SLI_Msk   (0x1UL /*<< TPI_LSR_SLI_Pos*/)
 
#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U
 
#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
 
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos   3U
 
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
 
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos   2U
 
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk   (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
 
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U
 
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
 
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U
 
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk   (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
 
#define CoreDebug_DSCSR_CDS_Pos   16U
 
#define CoreDebug_DSCSR_CDS_Msk   (1UL << CoreDebug_DSCSR_CDS_Pos)
 
#define CoreDebug_DSCSR_SBRSEL_Pos   1U
 
#define CoreDebug_DSCSR_SBRSEL_Msk   (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
 
#define CoreDebug_DSCSR_SBRSELEN_Pos   0U
 
#define CoreDebug_DSCSR_SBRSELEN_Msk   (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
 
#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U
 
#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
 
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos   3U
 
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
 
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos   2U
 
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk   (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
 
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U
 
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
 
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U
 
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk   (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
 
#define CoreDebug_DSCSR_CDS_Pos   16U
 
#define CoreDebug_DSCSR_CDS_Msk   (1UL << CoreDebug_DSCSR_CDS_Pos)
 
#define CoreDebug_DSCSR_SBRSEL_Pos   1U
 
#define CoreDebug_DSCSR_SBRSEL_Msk   (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
 
#define CoreDebug_DSCSR_SBRSELEN_Pos   0U
 
#define CoreDebug_DSCSR_SBRSELEN_Msk   (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
 
#define MPU_RBAR_ADDR_Pos   5U
 
#define MPU_RBAR_ADDR_Msk   (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)
 
#define MPU_RBAR_VALID_Pos   4U
 
#define MPU_RBAR_VALID_Msk   (1UL << MPU_RBAR_VALID_Pos)
 
#define MPU_RBAR_REGION_Pos   0U
 
#define MPU_RBAR_REGION_Msk   (0xFUL /*<< MPU_RBAR_REGION_Pos*/)
 
#define MPU_RASR_ATTRS_Pos   16U
 
#define MPU_RASR_ATTRS_Msk   (0xFFFFUL << MPU_RASR_ATTRS_Pos)
 
#define MPU_RASR_XN_Pos   28U
 
#define MPU_RASR_XN_Msk   (1UL << MPU_RASR_XN_Pos)
 
#define MPU_RASR_AP_Pos   24U
 
#define MPU_RASR_AP_Msk   (0x7UL << MPU_RASR_AP_Pos)
 
#define MPU_RASR_TEX_Pos   19U
 
#define MPU_RASR_TEX_Msk   (0x7UL << MPU_RASR_TEX_Pos)
 
#define MPU_RASR_S_Pos   18U
 
#define MPU_RASR_S_Msk   (1UL << MPU_RASR_S_Pos)
 
#define MPU_RASR_C_Pos   17U
 
#define MPU_RASR_C_Msk   (1UL << MPU_RASR_C_Pos)
 
#define MPU_RASR_B_Pos   16U
 
#define MPU_RASR_B_Msk   (1UL << MPU_RASR_B_Pos)
 
#define MPU_RASR_SRD_Pos   8U
 
#define MPU_RASR_SRD_Msk   (0xFFUL << MPU_RASR_SRD_Pos)
 
#define MPU_RASR_SIZE_Pos   1U
 
#define MPU_RASR_SIZE_Msk   (0x1FUL << MPU_RASR_SIZE_Pos)
 
#define MPU_RASR_ENABLE_Pos   0U
 
#define MPU_RASR_ENABLE_Msk   (1UL /*<< MPU_RASR_ENABLE_Pos*/)
 
#define MPU_RBAR_ADDR_Pos   5U
 
#define MPU_RBAR_ADDR_Msk   (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)
 
#define MPU_RBAR_VALID_Pos   4U
 
#define MPU_RBAR_VALID_Msk   (1UL << MPU_RBAR_VALID_Pos)
 
#define MPU_RBAR_REGION_Pos   0U
 
#define MPU_RBAR_REGION_Msk   (0xFUL /*<< MPU_RBAR_REGION_Pos*/)
 
#define MPU_RASR_ATTRS_Pos   16U
 
#define MPU_RASR_ATTRS_Msk   (0xFFFFUL << MPU_RASR_ATTRS_Pos)
 
#define MPU_RASR_XN_Pos   28U
 
#define MPU_RASR_XN_Msk   (1UL << MPU_RASR_XN_Pos)
 
#define MPU_RASR_AP_Pos   24U
 
#define MPU_RASR_AP_Msk   (0x7UL << MPU_RASR_AP_Pos)
 
#define MPU_RASR_TEX_Pos   19U
 
#define MPU_RASR_TEX_Msk   (0x7UL << MPU_RASR_TEX_Pos)
 
#define MPU_RASR_S_Pos   18U
 
#define MPU_RASR_S_Msk   (1UL << MPU_RASR_S_Pos)
 
#define MPU_RASR_C_Pos   17U
 
#define MPU_RASR_C_Msk   (1UL << MPU_RASR_C_Pos)
 
#define MPU_RASR_B_Pos   16U
 
#define MPU_RASR_B_Msk   (1UL << MPU_RASR_B_Pos)
 
#define MPU_RASR_SRD_Pos   8U
 
#define MPU_RASR_SRD_Msk   (0xFFUL << MPU_RASR_SRD_Pos)
 
#define MPU_RASR_SIZE_Pos   1U
 
#define MPU_RASR_SIZE_Msk   (0x1FUL << MPU_RASR_SIZE_Pos)
 
#define MPU_RASR_ENABLE_Pos   0U
 
#define MPU_RASR_ENABLE_Msk   (1UL /*<< MPU_RASR_ENABLE_Pos*/)
 
#define MPU_RBAR_ADDR_Pos   5U
 
#define MPU_RBAR_ADDR_Msk   (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)
 
#define MPU_RBAR_VALID_Pos   4U
 
#define MPU_RBAR_VALID_Msk   (1UL << MPU_RBAR_VALID_Pos)
 
#define MPU_RBAR_REGION_Pos   0U
 
#define MPU_RBAR_REGION_Msk   (0xFUL /*<< MPU_RBAR_REGION_Pos*/)
 
#define MPU_RASR_ATTRS_Pos   16U
 
#define MPU_RASR_ATTRS_Msk   (0xFFFFUL << MPU_RASR_ATTRS_Pos)
 
#define MPU_RASR_XN_Pos   28U
 
#define MPU_RASR_XN_Msk   (1UL << MPU_RASR_XN_Pos)
 
#define MPU_RASR_AP_Pos   24U
 
#define MPU_RASR_AP_Msk   (0x7UL << MPU_RASR_AP_Pos)
 
#define MPU_RASR_TEX_Pos   19U
 
#define MPU_RASR_TEX_Msk   (0x7UL << MPU_RASR_TEX_Pos)
 
#define MPU_RASR_S_Pos   18U
 
#define MPU_RASR_S_Msk   (1UL << MPU_RASR_S_Pos)
 
#define MPU_RASR_C_Pos   17U
 
#define MPU_RASR_C_Msk   (1UL << MPU_RASR_C_Pos)
 
#define MPU_RASR_B_Pos   16U
 
#define MPU_RASR_B_Msk   (1UL << MPU_RASR_B_Pos)
 
#define MPU_RASR_SRD_Pos   8U
 
#define MPU_RASR_SRD_Msk   (0xFFUL << MPU_RASR_SRD_Pos)
 
#define MPU_RASR_SIZE_Pos   1U
 
#define MPU_RASR_SIZE_Msk   (0x1FUL << MPU_RASR_SIZE_Pos)
 
#define MPU_RASR_ENABLE_Pos   0U
 
#define MPU_RASR_ENABLE_Msk   (1UL /*<< MPU_RASR_ENABLE_Pos*/)
 
#define MPU_RLAR_PXN_Pos   4U
 
#define MPU_RLAR_PXN_Msk   (1UL << MPU_RLAR_PXN_Pos)
 
#define MPU_RBAR_ADDR_Pos   5U
 
#define MPU_RBAR_ADDR_Msk   (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)
 
#define MPU_RBAR_VALID_Pos   4U
 
#define MPU_RBAR_VALID_Msk   (1UL << MPU_RBAR_VALID_Pos)
 
#define MPU_RBAR_REGION_Pos   0U
 
#define MPU_RBAR_REGION_Msk   (0xFUL /*<< MPU_RBAR_REGION_Pos*/)
 
#define MPU_RASR_ATTRS_Pos   16U
 
#define MPU_RASR_ATTRS_Msk   (0xFFFFUL << MPU_RASR_ATTRS_Pos)
 
#define MPU_RASR_XN_Pos   28U
 
#define MPU_RASR_XN_Msk   (1UL << MPU_RASR_XN_Pos)
 
#define MPU_RASR_AP_Pos   24U
 
#define MPU_RASR_AP_Msk   (0x7UL << MPU_RASR_AP_Pos)
 
#define MPU_RASR_TEX_Pos   19U
 
#define MPU_RASR_TEX_Msk   (0x7UL << MPU_RASR_TEX_Pos)
 
#define MPU_RASR_S_Pos   18U
 
#define MPU_RASR_S_Msk   (1UL << MPU_RASR_S_Pos)
 
#define MPU_RASR_C_Pos   17U
 
#define MPU_RASR_C_Msk   (1UL << MPU_RASR_C_Pos)
 
#define MPU_RASR_B_Pos   16U
 
#define MPU_RASR_B_Msk   (1UL << MPU_RASR_B_Pos)
 
#define MPU_RASR_SRD_Pos   8U
 
#define MPU_RASR_SRD_Msk   (0xFFUL << MPU_RASR_SRD_Pos)
 
#define MPU_RASR_SIZE_Pos   1U
 
#define MPU_RASR_SIZE_Msk   (0x1FUL << MPU_RASR_SIZE_Pos)
 
#define MPU_RASR_ENABLE_Pos   0U
 
#define MPU_RASR_ENABLE_Msk   (1UL /*<< MPU_RASR_ENABLE_Pos*/)
 
#define FPU_FPDSCR_FZ16_Pos   19U
 
#define FPU_FPDSCR_FZ16_Msk   (1UL << FPU_FPDSCR_FZ16_Pos)
 
#define FPU_FPDSCR_LTPSIZE_Pos   16U
 
#define FPU_FPDSCR_LTPSIZE_Msk   (7UL << FPU_FPDSCR_LTPSIZE_Pos)
 
#define FPU_MVFR0_FPRound_Pos   28U
 
#define FPU_MVFR0_FPRound_Msk   (0xFUL << FPU_MVFR0_FPRound_Pos)
 
#define FPU_MVFR0_FPSqrt_Pos   20U
 
#define FPU_MVFR0_FPSqrt_Msk   (0xFUL << FPU_MVFR0_FPSqrt_Pos)
 
#define FPU_MVFR0_FPDivide_Pos   16U
 
#define FPU_MVFR0_FPDivide_Msk   (0xFUL << FPU_MVFR0_FPDivide_Pos)
 
#define FPU_MVFR0_FPDP_Pos   8U
 
#define FPU_MVFR0_FPDP_Msk   (0xFUL << FPU_MVFR0_FPDP_Pos)
 
#define FPU_MVFR0_FPSP_Pos   4U
 
#define FPU_MVFR0_FPSP_Msk   (0xFUL << FPU_MVFR0_FPSP_Pos)
 
#define FPU_MVFR0_SIMDReg_Pos   0U
 
#define FPU_MVFR0_SIMDReg_Msk   (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/)
 
#define FPU_MVFR1_FMAC_Pos   28U
 
#define FPU_MVFR1_FMAC_Msk   (0xFUL << FPU_MVFR1_FMAC_Pos)
 
#define FPU_MVFR1_FPHP_Pos   24U
 
#define FPU_MVFR1_FPHP_Msk   (0xFUL << FPU_MVFR1_FPHP_Pos)
 
#define FPU_MVFR1_FP16_Pos   20U
 
#define FPU_MVFR1_FP16_Msk   (0xFUL << FPU_MVFR1_FP16_Pos)
 
#define FPU_MVFR1_MVE_Pos   8U
 
#define FPU_MVFR1_MVE_Msk   (0xFUL << FPU_MVFR1_MVE_Pos)
 
#define FPU_MVFR1_FPDNaN_Pos   4U
 
#define FPU_MVFR1_FPDNaN_Msk   (0xFUL << FPU_MVFR1_FPDNaN_Pos)
 
#define FPU_MVFR1_FPFtZ_Pos   0U
 
#define FPU_MVFR1_FPFtZ_Msk   (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/)
 
#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U
 
#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
 
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos   3U
 
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
 
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos   2U
 
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk   (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
 
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U
 
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
 
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U
 
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk   (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
 
#define CoreDebug_DSCSR_CDS_Pos   16U
 
#define CoreDebug_DSCSR_CDS_Msk   (1UL << CoreDebug_DSCSR_CDS_Pos)
 
#define CoreDebug_DSCSR_SBRSEL_Pos   1U
 
#define CoreDebug_DSCSR_SBRSEL_Msk   (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
 
#define CoreDebug_DSCSR_SBRSELEN_Pos   0U
 
#define CoreDebug_DSCSR_SBRSELEN_Msk   (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
 
#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U
 
#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
 
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos   3U
 
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
 
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos   2U
 
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk   (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
 
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U
 
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
 
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U
 
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk   (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
 
#define CoreDebug_DSCSR_CDS_Pos   16U
 
#define CoreDebug_DSCSR_CDS_Msk   (1UL << CoreDebug_DSCSR_CDS_Pos)
 
#define CoreDebug_DSCSR_SBRSEL_Pos   1U
 
#define CoreDebug_DSCSR_SBRSEL_Msk   (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
 
#define CoreDebug_DSCSR_SBRSELEN_Pos   0U
 
#define CoreDebug_DSCSR_SBRSELEN_Msk   (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
 
#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U
 
#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
 
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos   3U
 
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
 
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos   2U
 
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk   (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
 
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U
 
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
 
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U
 
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk   (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
 
#define CoreDebug_DSCSR_CDS_Pos   16U
 
#define CoreDebug_DSCSR_CDS_Msk   (1UL << CoreDebug_DSCSR_CDS_Pos)
 
#define CoreDebug_DSCSR_SBRSEL_Pos   1U
 
#define CoreDebug_DSCSR_SBRSEL_Msk   (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
 
#define CoreDebug_DSCSR_SBRSELEN_Pos   0U
 
#define CoreDebug_DSCSR_SBRSELEN_Msk   (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
 
#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U
 
#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
 
#define CoreDebug_DHCSR_S_FPD_Pos   23U
 
#define CoreDebug_DHCSR_S_FPD_Msk   (1UL << CoreDebug_DHCSR_S_FPD_Pos)
 
#define CoreDebug_DHCSR_S_SUIDE_Pos   22U
 
#define CoreDebug_DHCSR_S_SUIDE_Msk   (1UL << CoreDebug_DHCSR_S_SUIDE_Pos)
 
#define CoreDebug_DHCSR_S_NSUIDE_Pos   21U
 
#define CoreDebug_DHCSR_S_NSUIDE_Msk   (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos)
 
#define CoreDebug_DHCSR_S_SDE_Pos   20U
 
#define CoreDebug_DHCSR_S_SDE_Msk   (1UL << CoreDebug_DHCSR_S_SDE_Pos)
 
#define CoreDebug_DHCSR_C_PMOV_Pos   6U
 
#define CoreDebug_DHCSR_C_PMOV_Msk   (1UL << CoreDebug_DHCSR_C_PMOV_Pos)
 
#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos   19U
 
#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk   (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos)
 
#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos   17U
 
#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk   (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos)
 
#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos   3U
 
#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk   (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos)
 
#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos   1U
 
#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk   (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos)
 
#define CoreDebug_DAUTHCTRL_UIDEN_Pos   10U
 
#define CoreDebug_DAUTHCTRL_UIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos)
 
#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos   9U
 
#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk   (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos)
 
#define CoreDebug_DAUTHCTRL_FSDMA_Pos   8U
 
#define CoreDebug_DAUTHCTRL_FSDMA_Msk   (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos)
 
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos   3U
 
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
 
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos   2U
 
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk   (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
 
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U
 
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
 
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U
 
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk   (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
 
#define CoreDebug_DSCSR_CDS_Pos   16U
 
#define CoreDebug_DSCSR_CDS_Msk   (1UL << CoreDebug_DSCSR_CDS_Pos)
 
#define CoreDebug_DSCSR_SBRSEL_Pos   1U
 
#define CoreDebug_DSCSR_SBRSEL_Msk   (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
 
#define CoreDebug_DSCSR_SBRSELEN_Pos   0U
 
#define CoreDebug_DSCSR_SBRSELEN_Msk   (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
 
#define DCB_DHCSR_S_FPD_Pos   23U
 
#define DCB_DHCSR_S_FPD_Msk   (0x1UL << DCB_DHCSR_S_FPD_Pos)
 
#define DCB_DHCSR_S_SUIDE_Pos   22U
 
#define DCB_DHCSR_S_SUIDE_Msk   (0x1UL << DCB_DHCSR_S_SUIDE_Pos)
 
#define DCB_DHCSR_S_NSUIDE_Pos   21U
 
#define DCB_DHCSR_S_NSUIDE_Msk   (0x1UL << DCB_DHCSR_S_NSUIDE_Pos)
 
#define DCB_DHCSR_C_PMOV_Pos   6U
 
#define DCB_DHCSR_C_PMOV_Msk   (0x1UL << DCB_DHCSR_C_PMOV_Pos)
 
#define DCB_DSCEMCR_CLR_MON_REQ_Pos   19U
 
#define DCB_DSCEMCR_CLR_MON_REQ_Msk   (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos)
 
#define DCB_DSCEMCR_CLR_MON_PEND_Pos   17U
 
#define DCB_DSCEMCR_CLR_MON_PEND_Msk   (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos)
 
#define DCB_DSCEMCR_SET_MON_REQ_Pos   3U
 
#define DCB_DSCEMCR_SET_MON_REQ_Msk   (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos)
 
#define DCB_DSCEMCR_SET_MON_PEND_Pos   1U
 
#define DCB_DSCEMCR_SET_MON_PEND_Msk   (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos)
 
#define DCB_DAUTHCTRL_UIDEN_Pos   10U
 
#define DCB_DAUTHCTRL_UIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos)
 
#define DCB_DAUTHCTRL_UIDAPEN_Pos   9U
 
#define DCB_DAUTHCTRL_UIDAPEN_Msk   (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos)
 
#define DCB_DAUTHCTRL_FSDMA_Pos   8U
 
#define DCB_DAUTHCTRL_FSDMA_Msk   (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos)
 
#define DIB_DAUTHSTATUS_SUNID_Pos   22U
 
#define DIB_DAUTHSTATUS_SUNID_Msk   (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos )
 
#define DIB_DAUTHSTATUS_SUID_Pos   20U
 
#define DIB_DAUTHSTATUS_SUID_Msk   (0x3UL << DIB_DAUTHSTATUS_SUID_Pos )
 
#define DIB_DAUTHSTATUS_NSUNID_Pos   18U
 
#define DIB_DAUTHSTATUS_NSUNID_Msk   (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos )
 
#define DIB_DAUTHSTATUS_NSUID_Pos   16U
 
#define DIB_DAUTHSTATUS_NSUID_Msk   (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos )
 
#define MEMSYSCTL_BASE   (0xE001E000UL)
 
#define ERRBNK_BASE   (0xE001E100UL)
 
#define PWRMODCTL_BASE   (0xE001E300UL)
 
#define EWIC_BASE   (0xE001E400UL)
 
#define PRCCFGINF_BASE   (0xE001E700UL)
 
#define ICB   ((ICB_Type *) SCS_BASE )
 
#define MEMSYSCTL   ((MemSysCtl_Type *) MEMSYSCTL_BASE )
 
#define ERRBNK   ((ErrBnk_Type *) ERRBNK_BASE )
 
#define PWRMODCTL   ((PwrModCtl_Type *) PWRMODCTL_BASE )
 
#define EWIC   ((EWIC_Type *) EWIC_BASE )
 
#define PRCCFGINF   ((PrcCfgInf_Type *) PRCCFGINF_BASE )
 
#define EXC_RETURN_HANDLER   (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
 
#define EXC_RETURN_THREAD_MSP   (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
 
#define EXC_RETURN_THREAD_PSP   (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
 
#define EXC_RETURN_HANDLER   (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
 
#define EXC_RETURN_THREAD_MSP   (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
 
#define EXC_RETURN_THREAD_PSP   (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
 
#define EXC_RETURN_HANDLER   (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
 
#define EXC_RETURN_THREAD_MSP   (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
 
#define EXC_RETURN_THREAD_PSP   (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
 
#define EXC_RETURN_HANDLER   (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
 
#define EXC_RETURN_THREAD_MSP   (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
 
#define EXC_RETURN_THREAD_PSP   (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
 
#define ICB_ACTLR_DISCRITAXIRUW_Pos   27U
 
#define ICB_ACTLR_DISCRITAXIRUW_Msk   (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos)
 
#define ICB_ACTLR_DISCRITAXIRUR_Pos   15U
 
#define ICB_ACTLR_DISCRITAXIRUR_Msk   (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos)
 
#define ICB_ACTLR_EVENTBUSEN_Pos   14U
 
#define ICB_ACTLR_EVENTBUSEN_Msk   (1UL << ICB_ACTLR_EVENTBUSEN_Pos)
 
#define ICB_ACTLR_EVENTBUSEN_S_Pos   13U
 
#define ICB_ACTLR_EVENTBUSEN_S_Msk   (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos)
 
#define ICB_ACTLR_DISITMATBFLUSH_Pos   12U
 
#define ICB_ACTLR_DISITMATBFLUSH_Msk   (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos)
 
#define ICB_ACTLR_DISNWAMODE_Pos   11U
 
#define ICB_ACTLR_DISNWAMODE_Msk   (1UL << ICB_ACTLR_DISNWAMODE_Pos)
 
#define ICB_ACTLR_FPEXCODIS_Pos   10U
 
#define ICB_ACTLR_FPEXCODIS_Msk   (1UL << ICB_ACTLR_FPEXCODIS_Pos)
 
#define ICB_ICTR_INTLINESNUM_Pos   0U
 
#define ICB_ICTR_INTLINESNUM_Msk   (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/)
 
#define MEMSYSCTL_MSCR_CPWRDN_Pos   17U
 
#define MEMSYSCTL_MSCR_CPWRDN_Msk   (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos)
 
#define MEMSYSCTL_MSCR_DCCLEAN_Pos   16U
 
#define MEMSYSCTL_MSCR_DCCLEAN_Msk   (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos)
 
#define MEMSYSCTL_MSCR_ICACTIVE_Pos   13U
 
#define MEMSYSCTL_MSCR_ICACTIVE_Msk   (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos)
 
#define MEMSYSCTL_MSCR_DCACTIVE_Pos   12U
 
#define MEMSYSCTL_MSCR_DCACTIVE_Msk   (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos)
 
#define MEMSYSCTL_MSCR_EVECCFAULT_Pos   3U
 
#define MEMSYSCTL_MSCR_EVECCFAULT_Msk   (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos)
 
#define MEMSYSCTL_MSCR_FORCEWT_Pos   2U
 
#define MEMSYSCTL_MSCR_FORCEWT_Msk   (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos)
 
#define MEMSYSCTL_MSCR_ECCEN_Pos   1U
 
#define MEMSYSCTL_MSCR_ECCEN_Msk   (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos)
 
#define MEMSYSCTL_PFCR_DIS_NLP_Pos   7U
 
#define MEMSYSCTL_PFCR_DIS_NLP_Msk   (0x1UL << MEMSYSCTL_PFCR_DIS_NLP_Pos)
 
#define MEMSYSCTL_PFCR_ENABLE_Pos   0U
 
#define MEMSYSCTL_PFCR_ENABLE_Msk   (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/)
 
#define MEMSYSCTL_ITCMCR_SZ_Pos   3U
 
#define MEMSYSCTL_ITCMCR_SZ_Msk   (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos)
 
#define MEMSYSCTL_ITCMCR_EN_Pos   0U
 
#define MEMSYSCTL_ITCMCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/)
 
#define MEMSYSCTL_DTCMCR_SZ_Pos   3U
 
#define MEMSYSCTL_DTCMCR_SZ_Msk   (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos)
 
#define MEMSYSCTL_DTCMCR_EN_Pos   0U
 
#define MEMSYSCTL_DTCMCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/)
 
#define MEMSYSCTL_PAHBCR_SZ_Pos   1U
 
#define MEMSYSCTL_PAHBCR_SZ_Msk   (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos)
 
#define MEMSYSCTL_PAHBCR_EN_Pos   0U
 
#define MEMSYSCTL_PAHBCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/)
 
#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos   1U
 
#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk   (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos)
 
#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos   0U
 
#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk   (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/)
 
#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos   31U
 
#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk   (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos)
 
#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos   8U
 
#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk   (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos)
 
#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos   0U
 
#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk   (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/)
 
#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos   1U
 
#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk   (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos)
 
#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos   0U
 
#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk   (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/)
 
#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos   31U
 
#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk   (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos)
 
#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos   8U
 
#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk   (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos)
 
#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos   0U
 
#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk   (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/)
 
#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos   8U
 
#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk   (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos)
 
#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos   4U
 
#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk   (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos)
 
#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos   0U
 
#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk   (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/)
 
#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos   0U
 
#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk   (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/)
 
#define EWIC_EVENTSPR_EDBGREQ_Pos   2U
 
#define EWIC_EVENTSPR_EDBGREQ_Msk   (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos)
 
#define EWIC_EVENTSPR_NMI_Pos   1U
 
#define EWIC_EVENTSPR_NMI_Msk   (0x1UL << EWIC_EVENTSPR_NMI_Pos)
 
#define EWIC_EVENTSPR_EVENT_Pos   0U
 
#define EWIC_EVENTSPR_EVENT_Msk   (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/)
 
#define EWIC_EVENTMASKA_EDBGREQ_Pos   2U
 
#define EWIC_EVENTMASKA_EDBGREQ_Msk   (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos)
 
#define EWIC_EVENTMASKA_NMI_Pos   1U
 
#define EWIC_EVENTMASKA_NMI_Msk   (0x1UL << EWIC_EVENTMASKA_NMI_Pos)
 
#define EWIC_EVENTMASKA_EVENT_Pos   0U
 
#define EWIC_EVENTMASKA_EVENT_Msk   (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/)
 
#define EWIC_EVENTMASK_IRQ_Pos   0U
 
#define EWIC_EVENTMASK_IRQ_Msk   (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/)
 
#define ERRBNK_IEBR0_SWDEF_Pos   30U
 
#define ERRBNK_IEBR0_SWDEF_Msk   (0x3UL << ERRBNK_IEBR0_SWDEF_Pos)
 
#define ERRBNK_IEBR0_BANK_Pos   16U
 
#define ERRBNK_IEBR0_BANK_Msk   (0x1UL << ERRBNK_IEBR0_BANK_Pos)
 
#define ERRBNK_IEBR0_LOCATION_Pos   2U
 
#define ERRBNK_IEBR0_LOCATION_Msk   (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos)
 
#define ERRBNK_IEBR0_LOCKED_Pos   1U
 
#define ERRBNK_IEBR0_LOCKED_Msk   (0x1UL << ERRBNK_IEBR0_LOCKED_Pos)
 
#define ERRBNK_IEBR0_VALID_Pos   0U
 
#define ERRBNK_IEBR0_VALID_Msk   (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/)
 
#define ERRBNK_IEBR1_SWDEF_Pos   30U
 
#define ERRBNK_IEBR1_SWDEF_Msk   (0x3UL << ERRBNK_IEBR1_SWDEF_Pos)
 
#define ERRBNK_IEBR1_BANK_Pos   16U
 
#define ERRBNK_IEBR1_BANK_Msk   (0x1UL << ERRBNK_IEBR1_BANK_Pos)
 
#define ERRBNK_IEBR1_LOCATION_Pos   2U
 
#define ERRBNK_IEBR1_LOCATION_Msk   (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos)
 
#define ERRBNK_IEBR1_LOCKED_Pos   1U
 
#define ERRBNK_IEBR1_LOCKED_Msk   (0x1UL << ERRBNK_IEBR1_LOCKED_Pos)
 
#define ERRBNK_IEBR1_VALID_Pos   0U
 
#define ERRBNK_IEBR1_VALID_Msk   (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/)
 
#define ERRBNK_DEBR0_SWDEF_Pos   30U
 
#define ERRBNK_DEBR0_SWDEF_Msk   (0x3UL << ERRBNK_DEBR0_SWDEF_Pos)
 
#define ERRBNK_DEBR0_TYPE_Pos   17U
 
#define ERRBNK_DEBR0_TYPE_Msk   (0x1UL << ERRBNK_DEBR0_TYPE_Pos)
 
#define ERRBNK_DEBR0_BANK_Pos   16U
 
#define ERRBNK_DEBR0_BANK_Msk   (0x1UL << ERRBNK_DEBR0_BANK_Pos)
 
#define ERRBNK_DEBR0_LOCATION_Pos   2U
 
#define ERRBNK_DEBR0_LOCATION_Msk   (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos)
 
#define ERRBNK_DEBR0_LOCKED_Pos   1U
 
#define ERRBNK_DEBR0_LOCKED_Msk   (0x1UL << ERRBNK_DEBR0_LOCKED_Pos)
 
#define ERRBNK_DEBR0_VALID_Pos   0U
 
#define ERRBNK_DEBR0_VALID_Msk   (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/)
 
#define ERRBNK_DEBR1_SWDEF_Pos   30U
 
#define ERRBNK_DEBR1_SWDEF_Msk   (0x3UL << ERRBNK_DEBR1_SWDEF_Pos)
 
#define ERRBNK_DEBR1_TYPE_Pos   17U
 
#define ERRBNK_DEBR1_TYPE_Msk   (0x1UL << ERRBNK_DEBR1_TYPE_Pos)
 
#define ERRBNK_DEBR1_BANK_Pos   16U
 
#define ERRBNK_DEBR1_BANK_Msk   (0x1UL << ERRBNK_DEBR1_BANK_Pos)
 
#define ERRBNK_DEBR1_LOCATION_Pos   2U
 
#define ERRBNK_DEBR1_LOCATION_Msk   (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos)
 
#define ERRBNK_DEBR1_LOCKED_Pos   1U
 
#define ERRBNK_DEBR1_LOCKED_Msk   (0x1UL << ERRBNK_DEBR1_LOCKED_Pos)
 
#define ERRBNK_DEBR1_VALID_Pos   0U
 
#define ERRBNK_DEBR1_VALID_Msk   (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/)
 
#define ERRBNK_TEBR0_SWDEF_Pos   30U
 
#define ERRBNK_TEBR0_SWDEF_Msk   (0x3UL << ERRBNK_TEBR0_SWDEF_Pos)
 
#define ERRBNK_TEBR0_POISON_Pos   28U
 
#define ERRBNK_TEBR0_POISON_Msk   (0x1UL << ERRBNK_TEBR0_POISON_Pos)
 
#define ERRBNK_TEBR0_TYPE_Pos   27U
 
#define ERRBNK_TEBR0_TYPE_Msk   (0x1UL << ERRBNK_TEBR0_TYPE_Pos)
 
#define ERRBNK_TEBR0_BANK_Pos   24U
 
#define ERRBNK_TEBR0_BANK_Msk   (0x3UL << ERRBNK_TEBR0_BANK_Pos)
 
#define ERRBNK_TEBR0_LOCATION_Pos   2U
 
#define ERRBNK_TEBR0_LOCATION_Msk   (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos)
 
#define ERRBNK_TEBR0_LOCKED_Pos   1U
 
#define ERRBNK_TEBR0_LOCKED_Msk   (0x1UL << ERRBNK_TEBR0_LOCKED_Pos)
 
#define ERRBNK_TEBR0_VALID_Pos   0U
 
#define ERRBNK_TEBR0_VALID_Msk   (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/)
 
#define ERRBNK_TEBR1_SWDEF_Pos   30U
 
#define ERRBNK_TEBR1_SWDEF_Msk   (0x3UL << ERRBNK_TEBR1_SWDEF_Pos)
 
#define ERRBNK_TEBR1_POISON_Pos   28U
 
#define ERRBNK_TEBR1_POISON_Msk   (0x1UL << ERRBNK_TEBR1_POISON_Pos)
 
#define ERRBNK_TEBR1_TYPE_Pos   27U
 
#define ERRBNK_TEBR1_TYPE_Msk   (0x1UL << ERRBNK_TEBR1_TYPE_Pos)
 
#define ERRBNK_TEBR1_BANK_Pos   24U
 
#define ERRBNK_TEBR1_BANK_Msk   (0x3UL << ERRBNK_TEBR1_BANK_Pos)
 
#define ERRBNK_TEBR1_LOCATION_Pos   2U
 
#define ERRBNK_TEBR1_LOCATION_Msk   (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos)
 
#define ERRBNK_TEBR1_LOCKED_Pos   1U
 
#define ERRBNK_TEBR1_LOCKED_Msk   (0x1UL << ERRBNK_TEBR1_LOCKED_Pos)
 
#define ERRBNK_TEBR1_VALID_Pos   0U
 
#define ERRBNK_TEBR1_VALID_Msk   (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_PENDNMISET_Pos   31U
 
#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)
 
#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos
 
#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk
 
#define SCB_ICSR_PENDNMICLR_Pos   30U
 
#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_STTNS_Pos   24U
 
#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIS_Pos   14U
 
#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)
 
#define SCB_AIRCR_BFHFNMINS_Pos   13U
 
#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQS_Pos   3U
 
#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEPS_Pos   3U
 
#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_STKOFHFNMIGN_Pos   10U
 
#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U
 
#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U
 
#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTENA_Pos   19U
 
#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_NMIACT_Pos   5U
 
#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)
 
#define SCB_SHCSR_SECUREFAULTACT_Pos   4U
 
#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_HARDFAULTACT_Pos   2U
 
#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_NSACR_CP11_Pos   11U
 
#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)
 
#define SCB_NSACR_CP10_Pos   10U
 
#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)
 
#define SCB_CLIDR_LOUU_Pos   27U
 
#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)
 
#define SCB_CLIDR_LOC_Pos   24U
 
#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)
 
#define SCB_CTR_FORMAT_Pos   29U
 
#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)
 
#define SCB_CTR_CWG_Pos   24U
 
#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)
 
#define SCB_CTR_ERG_Pos   20U
 
#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)
 
#define SCB_CTR_DMINLINE_Pos   16U
 
#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)
 
#define SCB_CTR_IMINLINE_Pos   0U
 
#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
 
#define SCB_CCSIDR_WT_Pos   31U
 
#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)
 
#define SCB_CCSIDR_WB_Pos   30U
 
#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)
 
#define SCB_CCSIDR_RA_Pos   29U
 
#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)
 
#define SCB_CCSIDR_WA_Pos   28U
 
#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)
 
#define SCB_CCSIDR_NUMSETS_Pos   13U
 
#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
 
#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U
 
#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
 
#define SCB_CCSIDR_LINESIZE_Pos   0U
 
#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
 
#define SCB_CSSELR_LEVEL_Pos   1U
 
#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)
 
#define SCB_CSSELR_IND_Pos   0U
 
#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)
 
#define SCB_STIR_INTID_Pos   0U
 
#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
 
#define SCB_DCISW_WAY_Pos   30U
 
#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)
 
#define SCB_DCISW_SET_Pos   5U
 
#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)
 
#define SCB_DCCSW_WAY_Pos   30U
 
#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)
 
#define SCB_DCCSW_SET_Pos   5U
 
#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)
 
#define SCB_DCCISW_WAY_Pos   30U
 
#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)
 
#define SCB_DCCISW_SET_Pos   5U
 
#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_PENDNMISET_Pos   31U
 
#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)
 
#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos
 
#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk
 
#define SCB_ICSR_PENDNMICLR_Pos   30U
 
#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_STTNS_Pos   24U
 
#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIS_Pos   14U
 
#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)
 
#define SCB_AIRCR_BFHFNMINS_Pos   13U
 
#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)
 
#define SCB_AIRCR_SYSRESETREQS_Pos   3U
 
#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEPS_Pos   3U
 
#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_STKOFHFNMIGN_Pos   10U
 
#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U
 
#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_NMIACT_Pos   5U
 
#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)
 
#define SCB_SHCSR_HARDFAULTACT_Pos   2U
 
#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_PENDNMISET_Pos   31U
 
#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)
 
#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos
 
#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk
 
#define SCB_ICSR_PENDNMICLR_Pos   30U
 
#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_STTNS_Pos   24U
 
#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIS_Pos   14U
 
#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)
 
#define SCB_AIRCR_BFHFNMINS_Pos   13U
 
#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQS_Pos   3U
 
#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEPS_Pos   3U
 
#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_STKOFHFNMIGN_Pos   10U
 
#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U
 
#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U
 
#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTENA_Pos   19U
 
#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_NMIACT_Pos   5U
 
#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)
 
#define SCB_SHCSR_SECUREFAULTACT_Pos   4U
 
#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_HARDFAULTACT_Pos   2U
 
#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_NSACR_CP11_Pos   11U
 
#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)
 
#define SCB_NSACR_CP10_Pos   10U
 
#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)
 
#define SCB_NSACR_CPn_Pos   0U
 
#define SCB_NSACR_CPn_Msk   (1UL /*<< SCB_NSACR_CPn_Pos*/)
 
#define SCB_CLIDR_LOUU_Pos   27U
 
#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)
 
#define SCB_CLIDR_LOC_Pos   24U
 
#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)
 
#define SCB_CTR_FORMAT_Pos   29U
 
#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)
 
#define SCB_CTR_CWG_Pos   24U
 
#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)
 
#define SCB_CTR_ERG_Pos   20U
 
#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)
 
#define SCB_CTR_DMINLINE_Pos   16U
 
#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)
 
#define SCB_CTR_IMINLINE_Pos   0U
 
#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
 
#define SCB_CCSIDR_WT_Pos   31U
 
#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)
 
#define SCB_CCSIDR_WB_Pos   30U
 
#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)
 
#define SCB_CCSIDR_RA_Pos   29U
 
#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)
 
#define SCB_CCSIDR_WA_Pos   28U
 
#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)
 
#define SCB_CCSIDR_NUMSETS_Pos   13U
 
#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
 
#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U
 
#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
 
#define SCB_CCSIDR_LINESIZE_Pos   0U
 
#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
 
#define SCB_CSSELR_LEVEL_Pos   1U
 
#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)
 
#define SCB_CSSELR_IND_Pos   0U
 
#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)
 
#define SCB_STIR_INTID_Pos   0U
 
#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
 
#define SCB_DCISW_WAY_Pos   30U
 
#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)
 
#define SCB_DCISW_SET_Pos   5U
 
#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)
 
#define SCB_DCCSW_WAY_Pos   30U
 
#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)
 
#define SCB_DCCSW_SET_Pos   5U
 
#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)
 
#define SCB_DCCISW_WAY_Pos   30U
 
#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)
 
#define SCB_DCCISW_SET_Pos   5U
 
#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_PENDNMISET_Pos   31U
 
#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)
 
#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos
 
#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk
 
#define SCB_ICSR_PENDNMICLR_Pos   30U
 
#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_STTNS_Pos   24U
 
#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIS_Pos   14U
 
#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)
 
#define SCB_AIRCR_BFHFNMINS_Pos   13U
 
#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)
 
#define SCB_AIRCR_SYSRESETREQS_Pos   3U
 
#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEPS_Pos   3U
 
#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_STKOFHFNMIGN_Pos   10U
 
#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U
 
#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_NMIACT_Pos   5U
 
#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)
 
#define SCB_SHCSR_HARDFAULTACT_Pos   2U
 
#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_PENDNMISET_Pos   31U
 
#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)
 
#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos
 
#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk
 
#define SCB_ICSR_PENDNMICLR_Pos   30U
 
#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_STTNS_Pos   24U
 
#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIS_Pos   14U
 
#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)
 
#define SCB_AIRCR_BFHFNMINS_Pos   13U
 
#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQS_Pos   3U
 
#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEPS_Pos   3U
 
#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_STKOFHFNMIGN_Pos   10U
 
#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U
 
#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U
 
#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTENA_Pos   19U
 
#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_NMIACT_Pos   5U
 
#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)
 
#define SCB_SHCSR_SECUREFAULTACT_Pos   4U
 
#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_HARDFAULTACT_Pos   2U
 
#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_NSACR_CP11_Pos   11U
 
#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)
 
#define SCB_NSACR_CP10_Pos   10U
 
#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)
 
#define SCB_NSACR_CPn_Pos   0U
 
#define SCB_NSACR_CPn_Msk   (1UL /*<< SCB_NSACR_CPn_Pos*/)
 
#define SCB_CLIDR_LOUU_Pos   27U
 
#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)
 
#define SCB_CLIDR_LOC_Pos   24U
 
#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)
 
#define SCB_CTR_FORMAT_Pos   29U
 
#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)
 
#define SCB_CTR_CWG_Pos   24U
 
#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)
 
#define SCB_CTR_ERG_Pos   20U
 
#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)
 
#define SCB_CTR_DMINLINE_Pos   16U
 
#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)
 
#define SCB_CTR_IMINLINE_Pos   0U
 
#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
 
#define SCB_CCSIDR_WT_Pos   31U
 
#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)
 
#define SCB_CCSIDR_WB_Pos   30U
 
#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)
 
#define SCB_CCSIDR_RA_Pos   29U
 
#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)
 
#define SCB_CCSIDR_WA_Pos   28U
 
#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)
 
#define SCB_CCSIDR_NUMSETS_Pos   13U
 
#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
 
#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U
 
#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
 
#define SCB_CCSIDR_LINESIZE_Pos   0U
 
#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
 
#define SCB_CSSELR_LEVEL_Pos   1U
 
#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)
 
#define SCB_CSSELR_IND_Pos   0U
 
#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)
 
#define SCB_STIR_INTID_Pos   0U
 
#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
 
#define SCB_DCISW_WAY_Pos   30U
 
#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)
 
#define SCB_DCISW_SET_Pos   5U
 
#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)
 
#define SCB_DCCSW_WAY_Pos   30U
 
#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)
 
#define SCB_DCCSW_SET_Pos   5U
 
#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)
 
#define SCB_DCCISW_WAY_Pos   30U
 
#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)
 
#define SCB_DCCISW_SET_Pos   5U
 
#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_PENDNMISET_Pos   31U
 
#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)
 
#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos
 
#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk
 
#define SCB_ICSR_PENDNMICLR_Pos   30U
 
#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_STTNS_Pos   24U
 
#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIS_Pos   14U
 
#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)
 
#define SCB_AIRCR_BFHFNMINS_Pos   13U
 
#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQS_Pos   3U
 
#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEPS_Pos   3U
 
#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_STKOFHFNMIGN_Pos   10U
 
#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U
 
#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U
 
#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTENA_Pos   19U
 
#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_NMIACT_Pos   5U
 
#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)
 
#define SCB_SHCSR_SECUREFAULTACT_Pos   4U
 
#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_HARDFAULTACT_Pos   2U
 
#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_NSACR_CP11_Pos   11U
 
#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)
 
#define SCB_NSACR_CP10_Pos   10U
 
#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)
 
#define SCB_NSACR_CPn_Pos   0U
 
#define SCB_NSACR_CPn_Msk   (1UL /*<< SCB_NSACR_CPn_Pos*/)
 
#define SCB_CLIDR_LOUU_Pos   27U
 
#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)
 
#define SCB_CLIDR_LOC_Pos   24U
 
#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)
 
#define SCB_CTR_FORMAT_Pos   29U
 
#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)
 
#define SCB_CTR_CWG_Pos   24U
 
#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)
 
#define SCB_CTR_ERG_Pos   20U
 
#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)
 
#define SCB_CTR_DMINLINE_Pos   16U
 
#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)
 
#define SCB_CTR_IMINLINE_Pos   0U
 
#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
 
#define SCB_CCSIDR_WT_Pos   31U
 
#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)
 
#define SCB_CCSIDR_WB_Pos   30U
 
#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)
 
#define SCB_CCSIDR_RA_Pos   29U
 
#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)
 
#define SCB_CCSIDR_WA_Pos   28U
 
#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)
 
#define SCB_CCSIDR_NUMSETS_Pos   13U
 
#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
 
#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U
 
#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
 
#define SCB_CCSIDR_LINESIZE_Pos   0U
 
#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
 
#define SCB_CSSELR_LEVEL_Pos   1U
 
#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)
 
#define SCB_CSSELR_IND_Pos   0U
 
#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)
 
#define SCB_STIR_INTID_Pos   0U
 
#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
 
#define SCB_DCISW_WAY_Pos   30U
 
#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)
 
#define SCB_DCISW_SET_Pos   5U
 
#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)
 
#define SCB_DCCSW_WAY_Pos   30U
 
#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)
 
#define SCB_DCCSW_SET_Pos   5U
 
#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)
 
#define SCB_DCCISW_WAY_Pos   30U
 
#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)
 
#define SCB_DCCISW_SET_Pos   5U
 
#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_PENDNMISET_Pos   31U
 
#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)
 
#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos
 
#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk
 
#define SCB_ICSR_PENDNMICLR_Pos   30U
 
#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_STTNS_Pos   24U
 
#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIS_Pos   14U
 
#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)
 
#define SCB_AIRCR_BFHFNMINS_Pos   13U
 
#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQS_Pos   3U
 
#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEPS_Pos   3U
 
#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_STKOFHFNMIGN_Pos   10U
 
#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U
 
#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U
 
#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTENA_Pos   19U
 
#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_NMIACT_Pos   5U
 
#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)
 
#define SCB_SHCSR_SECUREFAULTACT_Pos   4U
 
#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_HARDFAULTACT_Pos   2U
 
#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_NSACR_CP11_Pos   11U
 
#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)
 
#define SCB_NSACR_CP10_Pos   10U
 
#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)
 
#define SCB_CLIDR_LOUU_Pos   27U
 
#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)
 
#define SCB_CLIDR_LOC_Pos   24U
 
#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)
 
#define SCB_CTR_FORMAT_Pos   29U
 
#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)
 
#define SCB_CTR_CWG_Pos   24U
 
#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)
 
#define SCB_CTR_ERG_Pos   20U
 
#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)
 
#define SCB_CTR_DMINLINE_Pos   16U
 
#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)
 
#define SCB_CTR_IMINLINE_Pos   0U
 
#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
 
#define SCB_CCSIDR_WT_Pos   31U
 
#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)
 
#define SCB_CCSIDR_WB_Pos   30U
 
#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)
 
#define SCB_CCSIDR_RA_Pos   29U
 
#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)
 
#define SCB_CCSIDR_WA_Pos   28U
 
#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)
 
#define SCB_CCSIDR_NUMSETS_Pos   13U
 
#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
 
#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U
 
#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
 
#define SCB_CCSIDR_LINESIZE_Pos   0U
 
#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
 
#define SCB_CSSELR_LEVEL_Pos   1U
 
#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)
 
#define SCB_CSSELR_IND_Pos   0U
 
#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)
 
#define SCB_STIR_INTID_Pos   0U
 
#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
 
#define SCB_DCISW_WAY_Pos   30U
 
#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)
 
#define SCB_DCISW_SET_Pos   5U
 
#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)
 
#define SCB_DCCSW_WAY_Pos   30U
 
#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)
 
#define SCB_DCCSW_SET_Pos   5U
 
#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)
 
#define SCB_DCCISW_WAY_Pos   30U
 
#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)
 
#define SCB_DCCISW_SET_Pos   5U
 
#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_CLIDR_LOUU_Pos   27U
 
#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)
 
#define SCB_CLIDR_LOC_Pos   24U
 
#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)
 
#define SCB_CTR_FORMAT_Pos   29U
 
#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)
 
#define SCB_CTR_CWG_Pos   24U
 
#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)
 
#define SCB_CTR_ERG_Pos   20U
 
#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)
 
#define SCB_CTR_DMINLINE_Pos   16U
 
#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)
 
#define SCB_CTR_IMINLINE_Pos   0U
 
#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
 
#define SCB_CCSIDR_WT_Pos   31U
 
#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)
 
#define SCB_CCSIDR_WB_Pos   30U
 
#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)
 
#define SCB_CCSIDR_RA_Pos   29U
 
#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)
 
#define SCB_CCSIDR_WA_Pos   28U
 
#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)
 
#define SCB_CCSIDR_NUMSETS_Pos   13U
 
#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
 
#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U
 
#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
 
#define SCB_CCSIDR_LINESIZE_Pos   0U
 
#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
 
#define SCB_CSSELR_LEVEL_Pos   1U
 
#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)
 
#define SCB_CSSELR_IND_Pos   0U
 
#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)
 
#define SCB_STIR_INTID_Pos   0U
 
#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
 
#define SCB_DCISW_WAY_Pos   30U
 
#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)
 
#define SCB_DCISW_SET_Pos   5U
 
#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)
 
#define SCB_DCCSW_WAY_Pos   30U
 
#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)
 
#define SCB_DCCSW_SET_Pos   5U
 
#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)
 
#define SCB_DCCISW_WAY_Pos   30U
 
#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)
 
#define SCB_DCCISW_SET_Pos   5U
 
#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)
 
#define SCB_ITCMCR_SZ_Pos   3U
 
#define SCB_ITCMCR_SZ_Msk   (0xFUL << SCB_ITCMCR_SZ_Pos)
 
#define SCB_ITCMCR_EN_Pos   0U
 
#define SCB_ITCMCR_EN_Msk   (1UL /*<< SCB_ITCMCR_EN_Pos*/)
 
#define SCB_DTCMCR_SZ_Pos   3U
 
#define SCB_DTCMCR_SZ_Msk   (0xFUL << SCB_DTCMCR_SZ_Pos)
 
#define SCB_DTCMCR_EN_Pos   0U
 
#define SCB_DTCMCR_EN_Msk   (1UL /*<< SCB_DTCMCR_EN_Pos*/)
 
#define SCB_CACR_FORCEWT_Pos   2U
 
#define SCB_CACR_FORCEWT_Msk   (1UL << SCB_CACR_FORCEWT_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_PENDNMISET_Pos   31U
 
#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)
 
#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos
 
#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk
 
#define SCB_ICSR_PENDNMICLR_Pos   30U
 
#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_STTNS_Pos   24U
 
#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIS_Pos   14U
 
#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)
 
#define SCB_AIRCR_BFHFNMINS_Pos   13U
 
#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQS_Pos   3U
 
#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEPS_Pos   3U
 
#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_STKOFHFNMIGN_Pos   10U
 
#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U
 
#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U
 
#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTENA_Pos   19U
 
#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_NMIACT_Pos   5U
 
#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)
 
#define SCB_SHCSR_SECUREFAULTACT_Pos   4U
 
#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_HARDFAULTACT_Pos   2U
 
#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_NSACR_CP11_Pos   11U
 
#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)
 
#define SCB_NSACR_CP10_Pos   10U
 
#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)
 
#define SCB_CLIDR_LOUU_Pos   27U
 
#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)
 
#define SCB_CLIDR_LOC_Pos   24U
 
#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)
 
#define SCB_CTR_FORMAT_Pos   29U
 
#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)
 
#define SCB_CTR_CWG_Pos   24U
 
#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)
 
#define SCB_CTR_ERG_Pos   20U
 
#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)
 
#define SCB_CTR_DMINLINE_Pos   16U
 
#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)
 
#define SCB_CTR_IMINLINE_Pos   0U
 
#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
 
#define SCB_CCSIDR_WT_Pos   31U
 
#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)
 
#define SCB_CCSIDR_WB_Pos   30U
 
#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)
 
#define SCB_CCSIDR_RA_Pos   29U
 
#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)
 
#define SCB_CCSIDR_WA_Pos   28U
 
#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)
 
#define SCB_CCSIDR_NUMSETS_Pos   13U
 
#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
 
#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U
 
#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
 
#define SCB_CCSIDR_LINESIZE_Pos   0U
 
#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
 
#define SCB_CSSELR_LEVEL_Pos   1U
 
#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)
 
#define SCB_CSSELR_IND_Pos   0U
 
#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)
 
#define SCB_STIR_INTID_Pos   0U
 
#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
 
#define SCB_DCISW_WAY_Pos   30U
 
#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)
 
#define SCB_DCISW_SET_Pos   5U
 
#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)
 
#define SCB_DCCSW_WAY_Pos   30U
 
#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)
 
#define SCB_DCCSW_SET_Pos   5U
 
#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)
 
#define SCB_DCCISW_WAY_Pos   30U
 
#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)
 
#define SCB_DCCISW_SET_Pos   5U
 
#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_PENDNMISET_Pos   31U
 
#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)
 
#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos
 
#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk
 
#define SCB_ICSR_PENDNMICLR_Pos   30U
 
#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_STTNS_Pos   24U
 
#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIS_Pos   14U
 
#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)
 
#define SCB_AIRCR_BFHFNMINS_Pos   13U
 
#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQS_Pos   3U
 
#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEPS_Pos   3U
 
#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_STKOFHFNMIGN_Pos   10U
 
#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U
 
#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U
 
#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTENA_Pos   19U
 
#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_NMIACT_Pos   5U
 
#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)
 
#define SCB_SHCSR_SECUREFAULTACT_Pos   4U
 
#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_HARDFAULTACT_Pos   2U
 
#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_NSACR_CP11_Pos   11U
 
#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)
 
#define SCB_NSACR_CP10_Pos   10U
 
#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)
 
#define SCB_NSACR_CPn_Pos   0U
 
#define SCB_NSACR_CPn_Msk   (1UL /*<< SCB_NSACR_CPn_Pos*/)
 
#define SCB_CLIDR_LOUU_Pos   27U
 
#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)
 
#define SCB_CLIDR_LOC_Pos   24U
 
#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)
 
#define SCB_CLIDR_IC_Pos   0U
 
#define SCB_CLIDR_IC_Msk   (1UL << SCB_CLIDR_IC_Pos)
 
#define SCB_CLIDR_DC_Pos   1U
 
#define SCB_CLIDR_DC_Msk   (1UL << SCB_CLIDR_DC_Pos)
 
#define SCB_CTR_FORMAT_Pos   29U
 
#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)
 
#define SCB_CTR_CWG_Pos   24U
 
#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)
 
#define SCB_CTR_ERG_Pos   20U
 
#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)
 
#define SCB_CTR_DMINLINE_Pos   16U
 
#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)
 
#define SCB_CTR_IMINLINE_Pos   0U
 
#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
 
#define SCB_CCSIDR_WT_Pos   31U
 
#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)
 
#define SCB_CCSIDR_WB_Pos   30U
 
#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)
 
#define SCB_CCSIDR_RA_Pos   29U
 
#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)
 
#define SCB_CCSIDR_WA_Pos   28U
 
#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)
 
#define SCB_CCSIDR_NUMSETS_Pos   13U
 
#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
 
#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U
 
#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
 
#define SCB_CCSIDR_LINESIZE_Pos   0U
 
#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
 
#define SCB_CSSELR_LEVEL_Pos   1U
 
#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)
 
#define SCB_CSSELR_IND_Pos   0U
 
#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)
 
#define SCB_STIR_INTID_Pos   0U
 
#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
 
#define SCB_DCISW_LEVEL_Pos   1U
 
#define SCB_DCISW_LEVEL_Msk   (7UL << SCB_DCISW_LEVEL_Pos)
 
#define SCB_DCISW_WAY_Pos   30U
 
#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)
 
#define SCB_DCISW_SET_Pos   5U
 
#define SCB_DCISW_SET_Msk   (0xFFUL << SCB_DCISW_SET_Pos)
 
#define SCB_DCCSW_LEVEL_Pos   1U
 
#define SCB_DCCSW_LEVEL_Msk   (7UL << SCB_DCCSW_LEVEL_Pos)
 
#define SCB_DCCSW_WAY_Pos   30U
 
#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)
 
#define SCB_DCCSW_SET_Pos   5U
 
#define SCB_DCCSW_SET_Msk   (0xFFUL << SCB_DCCSW_SET_Pos)
 
#define SCB_DCCISW_LEVEL_Pos   1U
 
#define SCB_DCCISW_LEVEL_Msk   (7UL << SCB_DCCISW_LEVEL_Pos)
 
#define SCB_DCCISW_WAY_Pos   30U
 
#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)
 
#define SCB_DCCISW_SET_Pos   5U
 
#define SCB_DCCISW_SET_Msk   (0xFFUL << SCB_DCCISW_SET_Pos)
 
#define SCB_ITCMCR_SZ_Pos   3U
 
#define SCB_ITCMCR_SZ_Msk   (0xFUL << SCB_ITCMCR_SZ_Pos)
 
#define SCB_ITCMCR_EN_Pos   0U
 
#define SCB_ITCMCR_EN_Msk   (1UL /*<< SCB_ITCMCR_EN_Pos*/)
 
#define SCB_DTCMCR_SZ_Pos   3U
 
#define SCB_DTCMCR_SZ_Msk   (0xFUL << SCB_DTCMCR_SZ_Pos)
 
#define SCB_DTCMCR_EN_Pos   0U
 
#define SCB_DTCMCR_EN_Msk   (1UL /*<< SCB_DTCMCR_EN_Pos*/)
 
#define SCB_CACR_DCCLEAN_Pos   16U
 
#define SCB_CACR_DCCLEAN_Msk   (1UL << SCB_CACR_FORCEWT_Pos)
 
#define SCB_CACR_ICACTIVE_Pos   13U
 
#define SCB_CACR_ICACTIVE_Msk   (1UL << SCB_CACR_FORCEWT_Pos)
 
#define SCB_CACR_DCACTIVE_Pos   12U
 
#define SCB_CACR_DCACTIVE_Msk   (1UL << SCB_CACR_FORCEWT_Pos)
 
#define SCB_CACR_FORCEWT_Pos   2U
 
#define SCB_CACR_FORCEWT_Msk   (1UL << SCB_CACR_FORCEWT_Pos)
 
#define SCB_AIRCR_IESB_Pos   5U
 
#define SCB_AIRCR_IESB_Msk   (1UL << SCB_AIRCR_IESB_Pos)
 
#define SCB_AIRCR_DIT_Pos   4U
 
#define SCB_AIRCR_DIT_Msk   (1UL << SCB_AIRCR_DIT_Pos)
 
#define SCB_CCR_TRD_Pos   20U
 
#define SCB_CCR_TRD_Msk   (1UL << SCB_CCR_TRD_Pos)
 
#define SCB_CCR_LOB_Pos   19U
 
#define SCB_CCR_LOB_Msk   (1UL << SCB_CCR_LOB_Pos)
 
#define SCB_DFSR_PMU_Pos   5U
 
#define SCB_DFSR_PMU_Msk   (1UL << SCB_DFSR_PMU_Pos)
 
#define SCB_NSACR_CP7_Pos   7U
 
#define SCB_NSACR_CP7_Msk   (1UL << SCB_NSACR_CP7_Pos)
 
#define SCB_NSACR_CP6_Pos   6U
 
#define SCB_NSACR_CP6_Msk   (1UL << SCB_NSACR_CP6_Pos)
 
#define SCB_NSACR_CP5_Pos   5U
 
#define SCB_NSACR_CP5_Msk   (1UL << SCB_NSACR_CP5_Pos)
 
#define SCB_NSACR_CP4_Pos   4U
 
#define SCB_NSACR_CP4_Msk   (1UL << SCB_NSACR_CP4_Pos)
 
#define SCB_NSACR_CP3_Pos   3U
 
#define SCB_NSACR_CP3_Msk   (1UL << SCB_NSACR_CP3_Pos)
 
#define SCB_NSACR_CP2_Pos   2U
 
#define SCB_NSACR_CP2_Msk   (1UL << SCB_NSACR_CP2_Pos)
 
#define SCB_NSACR_CP1_Pos   1U
 
#define SCB_NSACR_CP1_Msk   (1UL << SCB_NSACR_CP1_Pos)
 
#define SCB_NSACR_CP0_Pos   0U
 
#define SCB_NSACR_CP0_Msk   (1UL /*<< SCB_NSACR_CP0_Pos*/)
 
#define SCB_ID_DFR_UDE_Pos   28U
 
#define SCB_ID_DFR_UDE_Msk   (0xFUL << SCB_ID_DFR_UDE_Pos)
 
#define SCB_ID_DFR_MProfDbg_Pos   20U
 
#define SCB_ID_DFR_MProfDbg_Msk   (0xFUL << SCB_ID_DFR_MProfDbg_Pos)
 
#define SCB_RFSR_V_Pos   31U
 
#define SCB_RFSR_V_Msk   (1UL << SCB_RFSR_V_Pos)
 
#define SCB_RFSR_IS_Pos   16U
 
#define SCB_RFSR_IS_Msk   (0x7FFFUL << SCB_RFSR_IS_Pos)
 
#define SCB_RFSR_UET_Pos   0U
 
#define SCB_RFSR_UET_Msk   (3UL /*<< SCB_RFSR_UET_Pos*/)
 
#define SCB_AIRCR_IESB_Pos   5U
 
#define SCB_AIRCR_IESB_Msk   (1UL << SCB_AIRCR_IESB_Pos)
 
#define SCB_AIRCR_DIT_Pos   4U
 
#define SCB_AIRCR_DIT_Msk   (1UL << SCB_AIRCR_DIT_Pos)
 
#define SCB_CCR_TRD_Pos   20U
 
#define SCB_CCR_TRD_Msk   (1UL << SCB_CCR_TRD_Pos)
 
#define SCB_CCR_LOB_Pos   19U
 
#define SCB_CCR_LOB_Msk   (1UL << SCB_CCR_LOB_Pos)
 
#define SCB_DFSR_PMU_Pos   5U
 
#define SCB_DFSR_PMU_Msk   (1UL << SCB_DFSR_PMU_Pos)
 
#define SCB_NSACR_CP7_Pos   7U
 
#define SCB_NSACR_CP7_Msk   (1UL << SCB_NSACR_CP7_Pos)
 
#define SCB_NSACR_CP6_Pos   6U
 
#define SCB_NSACR_CP6_Msk   (1UL << SCB_NSACR_CP6_Pos)
 
#define SCB_NSACR_CP5_Pos   5U
 
#define SCB_NSACR_CP5_Msk   (1UL << SCB_NSACR_CP5_Pos)
 
#define SCB_NSACR_CP4_Pos   4U
 
#define SCB_NSACR_CP4_Msk   (1UL << SCB_NSACR_CP4_Pos)
 
#define SCB_NSACR_CP3_Pos   3U
 
#define SCB_NSACR_CP3_Msk   (1UL << SCB_NSACR_CP3_Pos)
 
#define SCB_NSACR_CP2_Pos   2U
 
#define SCB_NSACR_CP2_Msk   (1UL << SCB_NSACR_CP2_Pos)
 
#define SCB_NSACR_CP1_Pos   1U
 
#define SCB_NSACR_CP1_Msk   (1UL << SCB_NSACR_CP1_Pos)
 
#define SCB_NSACR_CP0_Pos   0U
 
#define SCB_NSACR_CP0_Msk   (1UL /*<< SCB_NSACR_CP0_Pos*/)
 
#define SCB_ID_DFR_UDE_Pos   28U
 
#define SCB_ID_DFR_UDE_Msk   (0xFUL << SCB_ID_DFR_UDE_Pos)
 
#define SCB_ID_DFR_MProfDbg_Pos   20U
 
#define SCB_ID_DFR_MProfDbg_Msk   (0xFUL << SCB_ID_DFR_MProfDbg_Pos)
 
#define SCB_RFSR_V_Pos   31U
 
#define SCB_RFSR_V_Msk   (1UL << SCB_RFSR_V_Pos)
 
#define SCB_RFSR_IS_Pos   16U
 
#define SCB_RFSR_IS_Msk   (0x7FFFUL << SCB_RFSR_IS_Pos)
 
#define SCB_RFSR_UET_Pos   0U
 
#define SCB_RFSR_UET_Msk   (3UL /*<< SCB_RFSR_UET_Pos*/)
 
#define SCB_AIRCR_IESB_Pos   5U
 
#define SCB_AIRCR_IESB_Msk   (1UL << SCB_AIRCR_IESB_Pos)
 
#define SCB_AIRCR_DIT_Pos   4U
 
#define SCB_AIRCR_DIT_Msk   (1UL << SCB_AIRCR_DIT_Pos)
 
#define SCB_CCR_TRD_Pos   20U
 
#define SCB_CCR_TRD_Msk   (1UL << SCB_CCR_TRD_Pos)
 
#define SCB_CCR_LOB_Pos   19U
 
#define SCB_CCR_LOB_Msk   (1UL << SCB_CCR_LOB_Pos)
 
#define SCB_DFSR_PMU_Pos   5U
 
#define SCB_DFSR_PMU_Msk   (1UL << SCB_DFSR_PMU_Pos)
 
#define SCB_NSACR_CP7_Pos   7U
 
#define SCB_NSACR_CP7_Msk   (1UL << SCB_NSACR_CP7_Pos)
 
#define SCB_NSACR_CP6_Pos   6U
 
#define SCB_NSACR_CP6_Msk   (1UL << SCB_NSACR_CP6_Pos)
 
#define SCB_NSACR_CP5_Pos   5U
 
#define SCB_NSACR_CP5_Msk   (1UL << SCB_NSACR_CP5_Pos)
 
#define SCB_NSACR_CP4_Pos   4U
 
#define SCB_NSACR_CP4_Msk   (1UL << SCB_NSACR_CP4_Pos)
 
#define SCB_NSACR_CP3_Pos   3U
 
#define SCB_NSACR_CP3_Msk   (1UL << SCB_NSACR_CP3_Pos)
 
#define SCB_NSACR_CP2_Pos   2U
 
#define SCB_NSACR_CP2_Msk   (1UL << SCB_NSACR_CP2_Pos)
 
#define SCB_NSACR_CP1_Pos   1U
 
#define SCB_NSACR_CP1_Msk   (1UL << SCB_NSACR_CP1_Pos)
 
#define SCB_NSACR_CP0_Pos   0U
 
#define SCB_NSACR_CP0_Msk   (1UL /*<< SCB_NSACR_CP0_Pos*/)
 
#define SCB_ID_DFR_UDE_Pos   28U
 
#define SCB_ID_DFR_UDE_Msk   (0xFUL << SCB_ID_DFR_UDE_Pos)
 
#define SCB_ID_DFR_MProfDbg_Pos   20U
 
#define SCB_ID_DFR_MProfDbg_Msk   (0xFUL << SCB_ID_DFR_MProfDbg_Pos)
 
#define SCB_RFSR_V_Pos   31U
 
#define SCB_RFSR_V_Msk   (1UL << SCB_RFSR_V_Pos)
 
#define SCB_RFSR_IS_Pos   16U
 
#define SCB_RFSR_IS_Msk   (0x7FFFUL << SCB_RFSR_IS_Pos)
 
#define SCB_RFSR_UET_Pos   0U
 
#define SCB_RFSR_UET_Msk   (3UL /*<< SCB_RFSR_UET_Pos*/)
 
#define TPI_ACPR_SWOSCALER_Pos   0U
 
#define TPI_ACPR_SWOSCALER_Msk   (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)
 
#define TPI_FFCR_EnFmt_Pos   0U
 
#define TPI_FFCR_EnFmt_Msk   (0x3UL << /*TPI_FFCR_EnFmt_Pos*/)
 
#define TPI_PSCR_PSCount_Pos   0U
 
#define TPI_PSCR_PSCount_Msk   (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)
 
#define TPI_LSR_nTT_Pos   1U
 
#define TPI_LSR_nTT_Msk   (0x1UL << TPI_LSR_nTT_Pos)
 
#define TPI_LSR_SLK_Pos   1U
 
#define TPI_LSR_SLK_Msk   (0x1UL << TPI_LSR_SLK_Pos)
 
#define TPI_LSR_SLI_Pos   0U
 
#define TPI_LSR_SLI_Msk   (0x1UL /*<< TPI_LSR_SLI_Pos*/)
 
#define MPU_RLAR_PXN_Pos   4U
 
#define MPU_RLAR_PXN_Msk   (1UL << MPU_RLAR_PXN_Pos)
 
#define FPU_FPDSCR_FZ16_Pos   19U
 
#define FPU_FPDSCR_FZ16_Msk   (1UL << FPU_FPDSCR_FZ16_Pos)
 
#define FPU_FPDSCR_LTPSIZE_Pos   16U
 
#define FPU_FPDSCR_LTPSIZE_Msk   (7UL << FPU_FPDSCR_LTPSIZE_Pos)
 
#define FPU_MVFR0_FPRound_Pos   28U
 
#define FPU_MVFR0_FPRound_Msk   (0xFUL << FPU_MVFR0_FPRound_Pos)
 
#define FPU_MVFR0_FPSqrt_Pos   20U
 
#define FPU_MVFR0_FPSqrt_Msk   (0xFUL << FPU_MVFR0_FPSqrt_Pos)
 
#define FPU_MVFR0_FPDivide_Pos   16U
 
#define FPU_MVFR0_FPDivide_Msk   (0xFUL << FPU_MVFR0_FPDivide_Pos)
 
#define FPU_MVFR0_FPDP_Pos   8U
 
#define FPU_MVFR0_FPDP_Msk   (0xFUL << FPU_MVFR0_FPDP_Pos)
 
#define FPU_MVFR0_FPSP_Pos   4U
 
#define FPU_MVFR0_FPSP_Msk   (0xFUL << FPU_MVFR0_FPSP_Pos)
 
#define FPU_MVFR0_SIMDReg_Pos   0U
 
#define FPU_MVFR0_SIMDReg_Msk   (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/)
 
#define FPU_MVFR1_FMAC_Pos   28U
 
#define FPU_MVFR1_FMAC_Msk   (0xFUL << FPU_MVFR1_FMAC_Pos)
 
#define FPU_MVFR1_FPHP_Pos   24U
 
#define FPU_MVFR1_FPHP_Msk   (0xFUL << FPU_MVFR1_FPHP_Pos)
 
#define FPU_MVFR1_FP16_Pos   20U
 
#define FPU_MVFR1_FP16_Msk   (0xFUL << FPU_MVFR1_FP16_Pos)
 
#define FPU_MVFR1_MVE_Pos   8U
 
#define FPU_MVFR1_MVE_Msk   (0xFUL << FPU_MVFR1_MVE_Pos)
 
#define FPU_MVFR1_FPDNaN_Pos   4U
 
#define FPU_MVFR1_FPDNaN_Msk   (0xFUL << FPU_MVFR1_FPDNaN_Pos)
 
#define FPU_MVFR1_FPFtZ_Pos   0U
 
#define FPU_MVFR1_FPFtZ_Msk   (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/)
 
#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U
 
#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
 
#define CoreDebug_DHCSR_S_FPD_Pos   23U
 
#define CoreDebug_DHCSR_S_FPD_Msk   (1UL << CoreDebug_DHCSR_S_FPD_Pos)
 
#define CoreDebug_DHCSR_S_SUIDE_Pos   22U
 
#define CoreDebug_DHCSR_S_SUIDE_Msk   (1UL << CoreDebug_DHCSR_S_SUIDE_Pos)
 
#define CoreDebug_DHCSR_S_NSUIDE_Pos   21U
 
#define CoreDebug_DHCSR_S_NSUIDE_Msk   (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos)
 
#define CoreDebug_DHCSR_S_SDE_Pos   20U
 
#define CoreDebug_DHCSR_S_SDE_Msk   (1UL << CoreDebug_DHCSR_S_SDE_Pos)
 
#define CoreDebug_DHCSR_C_PMOV_Pos   6U
 
#define CoreDebug_DHCSR_C_PMOV_Msk   (1UL << CoreDebug_DHCSR_C_PMOV_Pos)
 
#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos   19U
 
#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk   (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos)
 
#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos   17U
 
#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk   (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos)
 
#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos   3U
 
#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk   (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos)
 
#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos   1U
 
#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk   (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos)
 
#define CoreDebug_DAUTHCTRL_UIDEN_Pos   10U
 
#define CoreDebug_DAUTHCTRL_UIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos)
 
#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos   9U
 
#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk   (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos)
 
#define CoreDebug_DAUTHCTRL_FSDMA_Pos   8U
 
#define CoreDebug_DAUTHCTRL_FSDMA_Msk   (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos)
 
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos   3U
 
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
 
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos   2U
 
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk   (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
 
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U
 
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
 
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U
 
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk   (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
 
#define CoreDebug_DSCSR_CDS_Pos   16U
 
#define CoreDebug_DSCSR_CDS_Msk   (1UL << CoreDebug_DSCSR_CDS_Pos)
 
#define CoreDebug_DSCSR_SBRSEL_Pos   1U
 
#define CoreDebug_DSCSR_SBRSEL_Msk   (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
 
#define CoreDebug_DSCSR_SBRSELEN_Pos   0U
 
#define CoreDebug_DSCSR_SBRSELEN_Msk   (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
 
#define DCB_DHCSR_S_FPD_Pos   23U
 
#define DCB_DHCSR_S_FPD_Msk   (0x1UL << DCB_DHCSR_S_FPD_Pos)
 
#define DCB_DHCSR_S_SUIDE_Pos   22U
 
#define DCB_DHCSR_S_SUIDE_Msk   (0x1UL << DCB_DHCSR_S_SUIDE_Pos)
 
#define DCB_DHCSR_S_NSUIDE_Pos   21U
 
#define DCB_DHCSR_S_NSUIDE_Msk   (0x1UL << DCB_DHCSR_S_NSUIDE_Pos)
 
#define DCB_DHCSR_C_PMOV_Pos   6U
 
#define DCB_DHCSR_C_PMOV_Msk   (0x1UL << DCB_DHCSR_C_PMOV_Pos)
 
#define DCB_DSCEMCR_CLR_MON_REQ_Pos   19U
 
#define DCB_DSCEMCR_CLR_MON_REQ_Msk   (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos)
 
#define DCB_DSCEMCR_CLR_MON_PEND_Pos   17U
 
#define DCB_DSCEMCR_CLR_MON_PEND_Msk   (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos)
 
#define DCB_DSCEMCR_SET_MON_REQ_Pos   3U
 
#define DCB_DSCEMCR_SET_MON_REQ_Msk   (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos)
 
#define DCB_DSCEMCR_SET_MON_PEND_Pos   1U
 
#define DCB_DSCEMCR_SET_MON_PEND_Msk   (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos)
 
#define DCB_DAUTHCTRL_UIDEN_Pos   10U
 
#define DCB_DAUTHCTRL_UIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos)
 
#define DCB_DAUTHCTRL_UIDAPEN_Pos   9U
 
#define DCB_DAUTHCTRL_UIDAPEN_Msk   (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos)
 
#define DCB_DAUTHCTRL_FSDMA_Pos   8U
 
#define DCB_DAUTHCTRL_FSDMA_Msk   (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos)
 
#define DIB_DAUTHSTATUS_SUNID_Pos   22U
 
#define DIB_DAUTHSTATUS_SUNID_Msk   (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos )
 
#define DIB_DAUTHSTATUS_SUID_Pos   20U
 
#define DIB_DAUTHSTATUS_SUID_Msk   (0x3UL << DIB_DAUTHSTATUS_SUID_Pos )
 
#define DIB_DAUTHSTATUS_NSUNID_Pos   18U
 
#define DIB_DAUTHSTATUS_NSUNID_Msk   (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos )
 
#define DIB_DAUTHSTATUS_NSUID_Pos   16U
 
#define DIB_DAUTHSTATUS_NSUID_Msk   (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos )
 
#define ICB_ACTLR_DISCRITAXIRUW_Pos   27U
 
#define ICB_ACTLR_DISCRITAXIRUW_Msk   (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos)
 
#define ICB_ACTLR_DISCRITAXIRUR_Pos   15U
 
#define ICB_ACTLR_DISCRITAXIRUR_Msk   (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos)
 
#define ICB_ACTLR_EVENTBUSEN_Pos   14U
 
#define ICB_ACTLR_EVENTBUSEN_Msk   (1UL << ICB_ACTLR_EVENTBUSEN_Pos)
 
#define ICB_ACTLR_EVENTBUSEN_S_Pos   13U
 
#define ICB_ACTLR_EVENTBUSEN_S_Msk   (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos)
 
#define ICB_ACTLR_DISITMATBFLUSH_Pos   12U
 
#define ICB_ACTLR_DISITMATBFLUSH_Msk   (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos)
 
#define ICB_ACTLR_DISNWAMODE_Pos   11U
 
#define ICB_ACTLR_DISNWAMODE_Msk   (1UL << ICB_ACTLR_DISNWAMODE_Pos)
 
#define ICB_ACTLR_FPEXCODIS_Pos   10U
 
#define ICB_ACTLR_FPEXCODIS_Msk   (1UL << ICB_ACTLR_FPEXCODIS_Pos)
 
#define ICB_ICTR_INTLINESNUM_Pos   0U
 
#define ICB_ICTR_INTLINESNUM_Msk   (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/)
 
#define MEMSYSCTL_MSCR_CPWRDN_Pos   17U
 
#define MEMSYSCTL_MSCR_CPWRDN_Msk   (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos)
 
#define MEMSYSCTL_MSCR_DCCLEAN_Pos   16U
 
#define MEMSYSCTL_MSCR_DCCLEAN_Msk   (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos)
 
#define MEMSYSCTL_MSCR_ICACTIVE_Pos   13U
 
#define MEMSYSCTL_MSCR_ICACTIVE_Msk   (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos)
 
#define MEMSYSCTL_MSCR_DCACTIVE_Pos   12U
 
#define MEMSYSCTL_MSCR_DCACTIVE_Msk   (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos)
 
#define MEMSYSCTL_MSCR_EVECCFAULT_Pos   3U
 
#define MEMSYSCTL_MSCR_EVECCFAULT_Msk   (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos)
 
#define MEMSYSCTL_MSCR_FORCEWT_Pos   2U
 
#define MEMSYSCTL_MSCR_FORCEWT_Msk   (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos)
 
#define MEMSYSCTL_MSCR_ECCEN_Pos   1U
 
#define MEMSYSCTL_MSCR_ECCEN_Msk   (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos)
 
#define MEMSYSCTL_PFCR_ENABLE_Pos   0U
 
#define MEMSYSCTL_PFCR_ENABLE_Msk   (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/)
 
#define MEMSYSCTL_ITCMCR_SZ_Pos   3U
 
#define MEMSYSCTL_ITCMCR_SZ_Msk   (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos)
 
#define MEMSYSCTL_ITCMCR_EN_Pos   0U
 
#define MEMSYSCTL_ITCMCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/)
 
#define MEMSYSCTL_DTCMCR_SZ_Pos   3U
 
#define MEMSYSCTL_DTCMCR_SZ_Msk   (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos)
 
#define MEMSYSCTL_DTCMCR_EN_Pos   0U
 
#define MEMSYSCTL_DTCMCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/)
 
#define MEMSYSCTL_PAHBCR_SZ_Pos   1U
 
#define MEMSYSCTL_PAHBCR_SZ_Msk   (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos)
 
#define MEMSYSCTL_PAHBCR_EN_Pos   0U
 
#define MEMSYSCTL_PAHBCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/)
 
#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos   1U
 
#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk   (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos)
 
#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos   0U
 
#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk   (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/)
 
#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos   31U
 
#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk   (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos)
 
#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos   8U
 
#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk   (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos)
 
#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos   0U
 
#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk   (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/)
 
#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos   1U
 
#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk   (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos)
 
#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos   0U
 
#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk   (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/)
 
#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos   31U
 
#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk   (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos)
 
#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos   8U
 
#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk   (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos)
 
#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos   0U
 
#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk   (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/)
 
#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos   8U
 
#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk   (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos)
 
#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos   4U
 
#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk   (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos)
 
#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos   0U
 
#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk   (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/)
 
#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos   0U
 
#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk   (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/)
 
#define EWIC_EVENTSPR_EDBGREQ_Pos   2U
 
#define EWIC_EVENTSPR_EDBGREQ_Msk   (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos)
 
#define EWIC_EVENTSPR_NMI_Pos   1U
 
#define EWIC_EVENTSPR_NMI_Msk   (0x1UL << EWIC_EVENTSPR_NMI_Pos)
 
#define EWIC_EVENTSPR_EVENT_Pos   0U
 
#define EWIC_EVENTSPR_EVENT_Msk   (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/)
 
#define EWIC_EVENTMASKA_EDBGREQ_Pos   2U
 
#define EWIC_EVENTMASKA_EDBGREQ_Msk   (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos)
 
#define EWIC_EVENTMASKA_NMI_Pos   1U
 
#define EWIC_EVENTMASKA_NMI_Msk   (0x1UL << EWIC_EVENTMASKA_NMI_Pos)
 
#define EWIC_EVENTMASKA_EVENT_Pos   0U
 
#define EWIC_EVENTMASKA_EVENT_Msk   (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/)
 
#define EWIC_EVENTMASK_IRQ_Pos   0U
 
#define EWIC_EVENTMASK_IRQ_Msk   (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/)
 
#define ERRBNK_IEBR0_SWDEF_Pos   30U
 
#define ERRBNK_IEBR0_SWDEF_Msk   (0x3UL << ERRBNK_IEBR0_SWDEF_Pos)
 
#define ERRBNK_IEBR0_BANK_Pos   16U
 
#define ERRBNK_IEBR0_BANK_Msk   (0x1UL << ERRBNK_IEBR0_BANK_Pos)
 
#define ERRBNK_IEBR0_LOCATION_Pos   2U
 
#define ERRBNK_IEBR0_LOCATION_Msk   (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos)
 
#define ERRBNK_IEBR0_LOCKED_Pos   1U
 
#define ERRBNK_IEBR0_LOCKED_Msk   (0x1UL << ERRBNK_IEBR0_LOCKED_Pos)
 
#define ERRBNK_IEBR0_VALID_Pos   0U
 
#define ERRBNK_IEBR0_VALID_Msk   (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/)
 
#define ERRBNK_IEBR1_SWDEF_Pos   30U
 
#define ERRBNK_IEBR1_SWDEF_Msk   (0x3UL << ERRBNK_IEBR1_SWDEF_Pos)
 
#define ERRBNK_IEBR1_BANK_Pos   16U
 
#define ERRBNK_IEBR1_BANK_Msk   (0x1UL << ERRBNK_IEBR1_BANK_Pos)
 
#define ERRBNK_IEBR1_LOCATION_Pos   2U
 
#define ERRBNK_IEBR1_LOCATION_Msk   (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos)
 
#define ERRBNK_IEBR1_LOCKED_Pos   1U
 
#define ERRBNK_IEBR1_LOCKED_Msk   (0x1UL << ERRBNK_IEBR1_LOCKED_Pos)
 
#define ERRBNK_IEBR1_VALID_Pos   0U
 
#define ERRBNK_IEBR1_VALID_Msk   (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/)
 
#define ERRBNK_DEBR0_SWDEF_Pos   30U
 
#define ERRBNK_DEBR0_SWDEF_Msk   (0x3UL << ERRBNK_DEBR0_SWDEF_Pos)
 
#define ERRBNK_DEBR0_TYPE_Pos   17U
 
#define ERRBNK_DEBR0_TYPE_Msk   (0x1UL << ERRBNK_DEBR0_TYPE_Pos)
 
#define ERRBNK_DEBR0_BANK_Pos   16U
 
#define ERRBNK_DEBR0_BANK_Msk   (0x1UL << ERRBNK_DEBR0_BANK_Pos)
 
#define ERRBNK_DEBR0_LOCATION_Pos   2U
 
#define ERRBNK_DEBR0_LOCATION_Msk   (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos)
 
#define ERRBNK_DEBR0_LOCKED_Pos   1U
 
#define ERRBNK_DEBR0_LOCKED_Msk   (0x1UL << ERRBNK_DEBR0_LOCKED_Pos)
 
#define ERRBNK_DEBR0_VALID_Pos   0U
 
#define ERRBNK_DEBR0_VALID_Msk   (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/)
 
#define ERRBNK_DEBR1_SWDEF_Pos   30U
 
#define ERRBNK_DEBR1_SWDEF_Msk   (0x3UL << ERRBNK_DEBR1_SWDEF_Pos)
 
#define ERRBNK_DEBR1_TYPE_Pos   17U
 
#define ERRBNK_DEBR1_TYPE_Msk   (0x1UL << ERRBNK_DEBR1_TYPE_Pos)
 
#define ERRBNK_DEBR1_BANK_Pos   16U
 
#define ERRBNK_DEBR1_BANK_Msk   (0x1UL << ERRBNK_DEBR1_BANK_Pos)
 
#define ERRBNK_DEBR1_LOCATION_Pos   2U
 
#define ERRBNK_DEBR1_LOCATION_Msk   (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos)
 
#define ERRBNK_DEBR1_LOCKED_Pos   1U
 
#define ERRBNK_DEBR1_LOCKED_Msk   (0x1UL << ERRBNK_DEBR1_LOCKED_Pos)
 
#define ERRBNK_DEBR1_VALID_Pos   0U
 
#define ERRBNK_DEBR1_VALID_Msk   (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/)
 
#define ERRBNK_TEBR0_SWDEF_Pos   30U
 
#define ERRBNK_TEBR0_SWDEF_Msk   (0x3UL << ERRBNK_TEBR0_SWDEF_Pos)
 
#define ERRBNK_TEBR0_POISON_Pos   28U
 
#define ERRBNK_TEBR0_POISON_Msk   (0x1UL << ERRBNK_TEBR0_POISON_Pos)
 
#define ERRBNK_TEBR0_TYPE_Pos   27U
 
#define ERRBNK_TEBR0_TYPE_Msk   (0x1UL << ERRBNK_TEBR0_TYPE_Pos)
 
#define ERRBNK_TEBR0_BANK_Pos   24U
 
#define ERRBNK_TEBR0_BANK_Msk   (0x3UL << ERRBNK_TEBR0_BANK_Pos)
 
#define ERRBNK_TEBR0_LOCATION_Pos   2U
 
#define ERRBNK_TEBR0_LOCATION_Msk   (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos)
 
#define ERRBNK_TEBR0_LOCKED_Pos   1U
 
#define ERRBNK_TEBR0_LOCKED_Msk   (0x1UL << ERRBNK_TEBR0_LOCKED_Pos)
 
#define ERRBNK_TEBR0_VALID_Pos   0U
 
#define ERRBNK_TEBR0_VALID_Msk   (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/)
 
#define ERRBNK_TEBR1_SWDEF_Pos   30U
 
#define ERRBNK_TEBR1_SWDEF_Msk   (0x3UL << ERRBNK_TEBR1_SWDEF_Pos)
 
#define ERRBNK_TEBR1_POISON_Pos   28U
 
#define ERRBNK_TEBR1_POISON_Msk   (0x1UL << ERRBNK_TEBR1_POISON_Pos)
 
#define ERRBNK_TEBR1_TYPE_Pos   27U
 
#define ERRBNK_TEBR1_TYPE_Msk   (0x1UL << ERRBNK_TEBR1_TYPE_Pos)
 
#define ERRBNK_TEBR1_BANK_Pos   24U
 
#define ERRBNK_TEBR1_BANK_Msk   (0x3UL << ERRBNK_TEBR1_BANK_Pos)
 
#define ERRBNK_TEBR1_LOCATION_Pos   2U
 
#define ERRBNK_TEBR1_LOCATION_Msk   (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos)
 
#define ERRBNK_TEBR1_LOCKED_Pos   1U
 
#define ERRBNK_TEBR1_LOCKED_Msk   (0x1UL << ERRBNK_TEBR1_LOCKED_Pos)
 
#define ERRBNK_TEBR1_VALID_Pos   0U
 
#define ERRBNK_TEBR1_VALID_Msk   (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/)
 
#define TPI_ACPR_SWOSCALER_Pos   0U
 
#define TPI_ACPR_SWOSCALER_Msk   (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)
 
#define TPI_FFCR_EnFmt_Pos   0U
 
#define TPI_FFCR_EnFmt_Msk   (0x3UL << /*TPI_FFCR_EnFmt_Pos*/)
 
#define TPI_PSCR_PSCount_Pos   0U
 
#define TPI_PSCR_PSCount_Msk   (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)
 
#define TPI_LSR_nTT_Pos   1U
 
#define TPI_LSR_nTT_Msk   (0x1UL << TPI_LSR_nTT_Pos)
 
#define TPI_LSR_SLK_Pos   1U
 
#define TPI_LSR_SLK_Msk   (0x1UL << TPI_LSR_SLK_Pos)
 
#define TPI_LSR_SLI_Pos   0U
 
#define TPI_LSR_SLI_Msk   (0x1UL /*<< TPI_LSR_SLI_Pos*/)
 
#define MPU_RLAR_PXN_Pos   4U
 
#define MPU_RLAR_PXN_Msk   (1UL << MPU_RLAR_PXN_Pos)
 
#define FPU_FPDSCR_FZ16_Pos   19U
 
#define FPU_FPDSCR_FZ16_Msk   (1UL << FPU_FPDSCR_FZ16_Pos)
 
#define FPU_FPDSCR_LTPSIZE_Pos   16U
 
#define FPU_FPDSCR_LTPSIZE_Msk   (7UL << FPU_FPDSCR_LTPSIZE_Pos)
 
#define FPU_MVFR0_FPRound_Pos   28U
 
#define FPU_MVFR0_FPRound_Msk   (0xFUL << FPU_MVFR0_FPRound_Pos)
 
#define FPU_MVFR0_FPSqrt_Pos   20U
 
#define FPU_MVFR0_FPSqrt_Msk   (0xFUL << FPU_MVFR0_FPSqrt_Pos)
 
#define FPU_MVFR0_FPDivide_Pos   16U
 
#define FPU_MVFR0_FPDivide_Msk   (0xFUL << FPU_MVFR0_FPDivide_Pos)
 
#define FPU_MVFR0_FPDP_Pos   8U
 
#define FPU_MVFR0_FPDP_Msk   (0xFUL << FPU_MVFR0_FPDP_Pos)
 
#define FPU_MVFR0_FPSP_Pos   4U
 
#define FPU_MVFR0_FPSP_Msk   (0xFUL << FPU_MVFR0_FPSP_Pos)
 
#define FPU_MVFR0_SIMDReg_Pos   0U
 
#define FPU_MVFR0_SIMDReg_Msk   (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/)
 
#define FPU_MVFR1_FMAC_Pos   28U
 
#define FPU_MVFR1_FMAC_Msk   (0xFUL << FPU_MVFR1_FMAC_Pos)
 
#define FPU_MVFR1_FPHP_Pos   24U
 
#define FPU_MVFR1_FPHP_Msk   (0xFUL << FPU_MVFR1_FPHP_Pos)
 
#define FPU_MVFR1_FP16_Pos   20U
 
#define FPU_MVFR1_FP16_Msk   (0xFUL << FPU_MVFR1_FP16_Pos)
 
#define FPU_MVFR1_MVE_Pos   8U
 
#define FPU_MVFR1_MVE_Msk   (0xFUL << FPU_MVFR1_MVE_Pos)
 
#define FPU_MVFR1_FPDNaN_Pos   4U
 
#define FPU_MVFR1_FPDNaN_Msk   (0xFUL << FPU_MVFR1_FPDNaN_Pos)
 
#define FPU_MVFR1_FPFtZ_Pos   0U
 
#define FPU_MVFR1_FPFtZ_Msk   (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/)
 
#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U
 
#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
 
#define CoreDebug_DHCSR_S_FPD_Pos   23U
 
#define CoreDebug_DHCSR_S_FPD_Msk   (1UL << CoreDebug_DHCSR_S_FPD_Pos)
 
#define CoreDebug_DHCSR_S_SUIDE_Pos   22U
 
#define CoreDebug_DHCSR_S_SUIDE_Msk   (1UL << CoreDebug_DHCSR_S_SUIDE_Pos)
 
#define CoreDebug_DHCSR_S_NSUIDE_Pos   21U
 
#define CoreDebug_DHCSR_S_NSUIDE_Msk   (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos)
 
#define CoreDebug_DHCSR_S_SDE_Pos   20U
 
#define CoreDebug_DHCSR_S_SDE_Msk   (1UL << CoreDebug_DHCSR_S_SDE_Pos)
 
#define CoreDebug_DHCSR_C_PMOV_Pos   6U
 
#define CoreDebug_DHCSR_C_PMOV_Msk   (1UL << CoreDebug_DHCSR_C_PMOV_Pos)
 
#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos   19U
 
#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk   (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos)
 
#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos   17U
 
#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk   (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos)
 
#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos   3U
 
#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk   (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos)
 
#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos   1U
 
#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk   (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos)
 
#define CoreDebug_DAUTHCTRL_UIDEN_Pos   10U
 
#define CoreDebug_DAUTHCTRL_UIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos)
 
#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos   9U
 
#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk   (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos)
 
#define CoreDebug_DAUTHCTRL_FSDMA_Pos   8U
 
#define CoreDebug_DAUTHCTRL_FSDMA_Msk   (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos)
 
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos   3U
 
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
 
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos   2U
 
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk   (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
 
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U
 
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
 
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U
 
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk   (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
 
#define CoreDebug_DSCSR_CDS_Pos   16U
 
#define CoreDebug_DSCSR_CDS_Msk   (1UL << CoreDebug_DSCSR_CDS_Pos)
 
#define CoreDebug_DSCSR_SBRSEL_Pos   1U
 
#define CoreDebug_DSCSR_SBRSEL_Msk   (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
 
#define CoreDebug_DSCSR_SBRSELEN_Pos   0U
 
#define CoreDebug_DSCSR_SBRSELEN_Msk   (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
 
#define DCB_DHCSR_S_FPD_Pos   23U
 
#define DCB_DHCSR_S_FPD_Msk   (0x1UL << DCB_DHCSR_S_FPD_Pos)
 
#define DCB_DHCSR_S_SUIDE_Pos   22U
 
#define DCB_DHCSR_S_SUIDE_Msk   (0x1UL << DCB_DHCSR_S_SUIDE_Pos)
 
#define DCB_DHCSR_S_NSUIDE_Pos   21U
 
#define DCB_DHCSR_S_NSUIDE_Msk   (0x1UL << DCB_DHCSR_S_NSUIDE_Pos)
 
#define DCB_DHCSR_C_PMOV_Pos   6U
 
#define DCB_DHCSR_C_PMOV_Msk   (0x1UL << DCB_DHCSR_C_PMOV_Pos)
 
#define DCB_DSCEMCR_CLR_MON_REQ_Pos   19U
 
#define DCB_DSCEMCR_CLR_MON_REQ_Msk   (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos)
 
#define DCB_DSCEMCR_CLR_MON_PEND_Pos   17U
 
#define DCB_DSCEMCR_CLR_MON_PEND_Msk   (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos)
 
#define DCB_DSCEMCR_SET_MON_REQ_Pos   3U
 
#define DCB_DSCEMCR_SET_MON_REQ_Msk   (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos)
 
#define DCB_DSCEMCR_SET_MON_PEND_Pos   1U
 
#define DCB_DSCEMCR_SET_MON_PEND_Msk   (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos)
 
#define DCB_DAUTHCTRL_UIDEN_Pos   10U
 
#define DCB_DAUTHCTRL_UIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos)
 
#define DCB_DAUTHCTRL_UIDAPEN_Pos   9U
 
#define DCB_DAUTHCTRL_UIDAPEN_Msk   (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos)
 
#define DCB_DAUTHCTRL_FSDMA_Pos   8U
 
#define DCB_DAUTHCTRL_FSDMA_Msk   (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos)
 
#define DIB_DAUTHSTATUS_SUNID_Pos   22U
 
#define DIB_DAUTHSTATUS_SUNID_Msk   (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos )
 
#define DIB_DAUTHSTATUS_SUID_Pos   20U
 
#define DIB_DAUTHSTATUS_SUID_Msk   (0x3UL << DIB_DAUTHSTATUS_SUID_Pos )
 
#define DIB_DAUTHSTATUS_NSUNID_Pos   18U
 
#define DIB_DAUTHSTATUS_NSUNID_Msk   (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos )
 
#define DIB_DAUTHSTATUS_NSUID_Pos   16U
 
#define DIB_DAUTHSTATUS_NSUID_Msk   (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos )
 
#define MEMSYSCTL_BASE   (0xE001E000UL)
 
#define ERRBNK_BASE   (0xE001E100UL)
 
#define PWRMODCTL_BASE   (0xE001E300UL)
 
#define EWIC_BASE   (0xE001E400UL)
 
#define PRCCFGINF_BASE   (0xE001E700UL)
 
#define ICB   ((ICB_Type *) SCS_BASE )
 
#define MEMSYSCTL   ((MemSysCtl_Type *) MEMSYSCTL_BASE )
 
#define ERRBNK   ((ErrBnk_Type *) ERRBNK_BASE )
 
#define PWRMODCTL   ((PwrModCtl_Type *) PWRMODCTL_BASE )
 
#define EWIC   ((EWIC_Type *) EWIC_BASE )
 
#define PRCCFGINF   ((PrcCfgInf_Type *) PRCCFGINF_BASE )
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_AIRCR_VECTRESET_Pos   0U
 
#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_NONBASETHRDENA_Pos   0U
 
#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
 
#define SCB_AIRCR_VECTRESET_Pos   0U
 
#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_NONBASETHRDENA_Pos   0U
 
#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
 
#define SCB_AIRCR_VECTRESET_Pos   0U
 
#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_NONBASETHRDENA_Pos   0U
 
#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_VTOR_TBLBASE_Pos   29U
 
#define SCB_VTOR_TBLBASE_Msk   (1UL << SCB_VTOR_TBLBASE_Pos)
 
#define SCB_AIRCR_VECTRESET_Pos   0U
 
#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_NONBASETHRDENA_Pos   0U
 
#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
 
#define EXC_RETURN_HANDLER   (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
 
#define EXC_RETURN_THREAD_MSP   (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
 
#define EXC_RETURN_THREAD_PSP   (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
 
#define MPU_RBAR_ADDR_Pos   8U
 
#define MPU_RBAR_ADDR_Msk   (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)
 
#define MPU_RBAR_VALID_Pos   4U
 
#define MPU_RBAR_VALID_Msk   (1UL << MPU_RBAR_VALID_Pos)
 
#define MPU_RBAR_REGION_Pos   0U
 
#define MPU_RBAR_REGION_Msk   (0xFUL /*<< MPU_RBAR_REGION_Pos*/)
 
#define MPU_RASR_ATTRS_Pos   16U
 
#define MPU_RASR_ATTRS_Msk   (0xFFFFUL << MPU_RASR_ATTRS_Pos)
 
#define MPU_RASR_XN_Pos   28U
 
#define MPU_RASR_XN_Msk   (1UL << MPU_RASR_XN_Pos)
 
#define MPU_RASR_AP_Pos   24U
 
#define MPU_RASR_AP_Msk   (0x7UL << MPU_RASR_AP_Pos)
 
#define MPU_RASR_TEX_Pos   19U
 
#define MPU_RASR_TEX_Msk   (0x7UL << MPU_RASR_TEX_Pos)
 
#define MPU_RASR_S_Pos   18U
 
#define MPU_RASR_S_Msk   (1UL << MPU_RASR_S_Pos)
 
#define MPU_RASR_C_Pos   17U
 
#define MPU_RASR_C_Msk   (1UL << MPU_RASR_C_Pos)
 
#define MPU_RASR_B_Pos   16U
 
#define MPU_RASR_B_Msk   (1UL << MPU_RASR_B_Pos)
 
#define MPU_RASR_SRD_Pos   8U
 
#define MPU_RASR_SRD_Msk   (0xFFUL << MPU_RASR_SRD_Pos)
 
#define MPU_RASR_SIZE_Pos   1U
 
#define MPU_RASR_SIZE_Msk   (0x1FUL << MPU_RASR_SIZE_Pos)
 
#define MPU_RASR_ENABLE_Pos   0U
 
#define MPU_RASR_ENABLE_Msk   (1UL /*<< MPU_RASR_ENABLE_Pos*/)
 
#define EXC_RETURN_HANDLER   (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
 
#define EXC_RETURN_THREAD_MSP   (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
 
#define EXC_RETURN_THREAD_PSP   (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
 
#define EXC_RETURN_HANDLER   (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
 
#define EXC_RETURN_THREAD_MSP   (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
 
#define EXC_RETURN_THREAD_PSP   (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
 
#define SCnSCB_ACTLR_DISMCYCINT_Pos   0U
 
#define SCnSCB_ACTLR_DISMCYCINT_Msk   (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)
 
#define MPU_RBAR_ADDR_Pos   8U
 
#define MPU_RBAR_ADDR_Msk   (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)
 
#define MPU_RBAR_VALID_Pos   4U
 
#define MPU_RBAR_VALID_Msk   (1UL << MPU_RBAR_VALID_Pos)
 
#define MPU_RBAR_REGION_Pos   0U
 
#define MPU_RBAR_REGION_Msk   (0xFUL /*<< MPU_RBAR_REGION_Pos*/)
 
#define MPU_RASR_ATTRS_Pos   16U
 
#define MPU_RASR_ATTRS_Msk   (0xFFFFUL << MPU_RASR_ATTRS_Pos)
 
#define MPU_RASR_XN_Pos   28U
 
#define MPU_RASR_XN_Msk   (1UL << MPU_RASR_XN_Pos)
 
#define MPU_RASR_AP_Pos   24U
 
#define MPU_RASR_AP_Msk   (0x7UL << MPU_RASR_AP_Pos)
 
#define MPU_RASR_TEX_Pos   19U
 
#define MPU_RASR_TEX_Msk   (0x7UL << MPU_RASR_TEX_Pos)
 
#define MPU_RASR_S_Pos   18U
 
#define MPU_RASR_S_Msk   (1UL << MPU_RASR_S_Pos)
 
#define MPU_RASR_C_Pos   17U
 
#define MPU_RASR_C_Msk   (1UL << MPU_RASR_C_Pos)
 
#define MPU_RASR_B_Pos   16U
 
#define MPU_RASR_B_Msk   (1UL << MPU_RASR_B_Pos)
 
#define MPU_RASR_SRD_Pos   8U
 
#define MPU_RASR_SRD_Msk   (0xFFUL << MPU_RASR_SRD_Pos)
 
#define MPU_RASR_SIZE_Pos   1U
 
#define MPU_RASR_SIZE_Msk   (0x1FUL << MPU_RASR_SIZE_Pos)
 
#define MPU_RASR_ENABLE_Pos   0U
 
#define MPU_RASR_ENABLE_Msk   (1UL /*<< MPU_RASR_ENABLE_Pos*/)
 
#define EXC_RETURN_HANDLER   (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
 
#define EXC_RETURN_THREAD_MSP   (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
 
#define EXC_RETURN_THREAD_PSP   (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
 
#define SCB_ITCMCR_RETEN_Pos   2U
 
#define SCB_ITCMCR_RETEN_Msk   (1UL << SCB_ITCMCR_RETEN_Pos)
 
#define SCB_ITCMCR_RMW_Pos   1U
 
#define SCB_ITCMCR_RMW_Msk   (1UL << SCB_ITCMCR_RMW_Pos)
 
#define SCB_DTCMCR_RETEN_Pos   2U
 
#define SCB_DTCMCR_RETEN_Msk   (1UL << SCB_DTCMCR_RETEN_Pos)
 
#define SCB_DTCMCR_RMW_Pos   1U
 
#define SCB_DTCMCR_RMW_Msk   (1UL << SCB_DTCMCR_RMW_Pos)
 
#define SCB_AHBPCR_SZ_Pos   1U
 
#define SCB_AHBPCR_SZ_Msk   (7UL << SCB_AHBPCR_SZ_Pos)
 
#define SCB_AHBPCR_EN_Pos   0U
 
#define SCB_AHBPCR_EN_Msk   (1UL /*<< SCB_AHBPCR_EN_Pos*/)
 
#define SCB_CACR_ECCEN_Pos   1U
 
#define SCB_CACR_ECCEN_Msk   (1UL << SCB_CACR_ECCEN_Pos)
 
#define SCB_CACR_ECCDIS_Pos   1U
 
#define SCB_CACR_ECCDIS_Msk   (1UL << SCB_CACR_ECCDIS_Pos)
 
#define SCB_CACR_SIWT_Pos   0U
 
#define SCB_CACR_SIWT_Msk   (1UL /*<< SCB_CACR_SIWT_Pos*/)
 
#define SCB_AHBSCR_INITCOUNT_Pos   11U
 
#define SCB_AHBSCR_INITCOUNT_Msk   (0x1FUL << SCB_AHBSCR_INITCOUNT_Pos)
 
#define SCB_AHBSCR_TPRI_Pos   2U
 
#define SCB_AHBSCR_TPRI_Msk   (0x1FFUL << SCB_AHBSCR_TPRI_Pos)
 
#define SCB_AHBSCR_CTL_Pos   0U
 
#define SCB_AHBSCR_CTL_Msk   (3UL /*<< SCB_AHBSCR_CTL_Pos*/)
 
#define SCB_ABFSR_AXIMTYPE_Pos   8U
 
#define SCB_ABFSR_AXIMTYPE_Msk   (3UL << SCB_ABFSR_AXIMTYPE_Pos)
 
#define SCB_ABFSR_EPPB_Pos   4U
 
#define SCB_ABFSR_EPPB_Msk   (1UL << SCB_ABFSR_EPPB_Pos)
 
#define SCB_ABFSR_AXIM_Pos   3U
 
#define SCB_ABFSR_AXIM_Msk   (1UL << SCB_ABFSR_AXIM_Pos)
 
#define SCB_ABFSR_AHBP_Pos   2U
 
#define SCB_ABFSR_AHBP_Msk   (1UL << SCB_ABFSR_AHBP_Pos)
 
#define SCB_ABFSR_DTCM_Pos   1U
 
#define SCB_ABFSR_DTCM_Msk   (1UL << SCB_ABFSR_DTCM_Pos)
 
#define SCB_ABFSR_ITCM_Pos   0U
 
#define SCB_ABFSR_ITCM_Msk   (1UL /*<< SCB_ABFSR_ITCM_Pos*/)
 

Detailed Description

Type definitions for the System Control Block Registers.

Macro Definition Documentation

◆ CoreDebug_DAUTHCTRL_FSDMA_Msk [1/3]

#define CoreDebug_DAUTHCTRL_FSDMA_Msk   (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos)
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CoreDebug DAUTHCTRL: FSDMA, Mask
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CoreDebug DAUTHCTRL: FSDMA, Mask
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CoreDebug DAUTHCTRL: FSDMA, Mask

◆ CoreDebug_DAUTHCTRL_FSDMA_Msk [2/3]

#define CoreDebug_DAUTHCTRL_FSDMA_Msk   (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos)
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CoreDebug DAUTHCTRL: FSDMA, Mask
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CoreDebug DAUTHCTRL: FSDMA, Mask

◆ CoreDebug_DAUTHCTRL_FSDMA_Msk [3/3]

#define CoreDebug_DAUTHCTRL_FSDMA_Msk   (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos)
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CoreDebug DAUTHCTRL: FSDMA, Mask

◆ CoreDebug_DAUTHCTRL_FSDMA_Pos [1/3]

#define CoreDebug_DAUTHCTRL_FSDMA_Pos   8U
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CoreDebug DAUTHCTRL: FSDMA, Position
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CoreDebug DAUTHCTRL: FSDMA, Position
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CoreDebug DAUTHCTRL: FSDMA, Position

◆ CoreDebug_DAUTHCTRL_FSDMA_Pos [2/3]

#define CoreDebug_DAUTHCTRL_FSDMA_Pos   8U
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CoreDebug DAUTHCTRL: FSDMA, Position
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CoreDebug DAUTHCTRL: FSDMA, Position

◆ CoreDebug_DAUTHCTRL_FSDMA_Pos [3/3]

#define CoreDebug_DAUTHCTRL_FSDMA_Pos   8U
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CoreDebug DAUTHCTRL: FSDMA, Position

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Msk [1/8]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
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CoreDebug DAUTHCTRL: INTSPIDEN Mask
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CoreDebug DAUTHCTRL: INTSPIDEN Mask
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CoreDebug DAUTHCTRL: INTSPIDEN Mask
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CoreDebug DAUTHCTRL: INTSPIDEN Mask
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CoreDebug DAUTHCTRL: INTSPIDEN Mask
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CoreDebug DAUTHCTRL: INTSPIDEN Mask
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CoreDebug DAUTHCTRL: INTSPIDEN Mask
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CoreDebug DAUTHCTRL: INTSPIDEN Mask

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Msk [2/8]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
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CoreDebug DAUTHCTRL: INTSPIDEN Mask
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CoreDebug DAUTHCTRL: INTSPIDEN Mask
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CoreDebug DAUTHCTRL: INTSPIDEN Mask
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CoreDebug DAUTHCTRL: INTSPIDEN Mask
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CoreDebug DAUTHCTRL: INTSPIDEN Mask
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CoreDebug DAUTHCTRL: INTSPIDEN Mask
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CoreDebug DAUTHCTRL: INTSPIDEN Mask

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Msk [3/8]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Mask
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CoreDebug DAUTHCTRL: INTSPIDEN Mask
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CoreDebug DAUTHCTRL: INTSPIDEN Mask
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CoreDebug DAUTHCTRL: INTSPIDEN Mask
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CoreDebug DAUTHCTRL: INTSPIDEN Mask

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Msk [4/8]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
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CoreDebug DAUTHCTRL: INTSPIDEN Mask
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CoreDebug DAUTHCTRL: INTSPIDEN Mask
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CoreDebug DAUTHCTRL: INTSPIDEN Mask
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CoreDebug DAUTHCTRL: INTSPIDEN Mask
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CoreDebug DAUTHCTRL: INTSPIDEN Mask

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Msk [5/8]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
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CoreDebug DAUTHCTRL: INTSPIDEN Mask
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CoreDebug DAUTHCTRL: INTSPIDEN Mask
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CoreDebug DAUTHCTRL: INTSPIDEN Mask
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CoreDebug DAUTHCTRL: INTSPIDEN Mask

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Msk [6/8]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Mask
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CoreDebug DAUTHCTRL: INTSPIDEN Mask
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CoreDebug DAUTHCTRL: INTSPIDEN Mask

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Msk [7/8]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
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CoreDebug DAUTHCTRL: INTSPIDEN Mask
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CoreDebug DAUTHCTRL: INTSPIDEN Mask

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Msk [8/8]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
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CoreDebug DAUTHCTRL: INTSPIDEN Mask

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Pos [1/8]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U
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CoreDebug DAUTHCTRL: INTSPIDEN Position
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CoreDebug DAUTHCTRL: INTSPIDEN Position
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CoreDebug DAUTHCTRL: INTSPIDEN Position
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CoreDebug DAUTHCTRL: INTSPIDEN Position
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CoreDebug DAUTHCTRL: INTSPIDEN Position
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CoreDebug DAUTHCTRL: INTSPIDEN Position
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CoreDebug DAUTHCTRL: INTSPIDEN Position
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CoreDebug DAUTHCTRL: INTSPIDEN Position

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Pos [2/8]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Pos [3/8]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Pos [4/8]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Pos [5/8]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Pos [6/8]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Pos [7/8]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Pos [8/8]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk [1/8]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk [2/8]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk [3/8]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk [4/8]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk [5/8]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk [6/8]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk [7/8]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk [8/8]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos [1/8]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos   3U
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos [2/8]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos   3U
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos [3/8]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos   3U
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos [4/8]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos   3U
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos [5/8]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos   3U
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos [6/8]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos   3U
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos [7/8]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos   3U
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos [8/8]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos   3U
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Msk [1/8]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk   (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Msk [2/8]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk   (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Msk [3/8]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk   (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Msk [4/8]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk   (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Msk [5/8]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk   (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Msk [6/8]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk   (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Msk [7/8]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk   (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Msk [8/8]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk   (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Pos [1/8]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Pos [2/8]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Pos [3/8]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Pos [4/8]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Pos [5/8]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Pos [6/8]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Pos [7/8]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Pos [8/8]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk [1/8]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk   (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk [2/8]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk   (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk [3/8]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk   (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk [4/8]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk   (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk [5/8]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk   (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk [6/8]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk   (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk [7/8]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk   (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk [8/8]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk   (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos [1/8]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos   2U
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos [2/8]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos   2U
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos [3/8]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos   2U
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos [4/8]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos   2U
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos [5/8]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos   2U
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos [6/8]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos   2U
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos [7/8]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos   2U
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos [8/8]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos   2U
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position

◆ CoreDebug_DAUTHCTRL_UIDAPEN_Msk [1/3]

#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk   (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos)
Deprecated
CoreDebug DAUTHCTRL: UIDAPEN, Mask
Deprecated
CoreDebug DAUTHCTRL: UIDAPEN, Mask
Deprecated
CoreDebug DAUTHCTRL: UIDAPEN, Mask

◆ CoreDebug_DAUTHCTRL_UIDAPEN_Msk [2/3]

#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk   (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos)
Deprecated
CoreDebug DAUTHCTRL: UIDAPEN, Mask
Deprecated
CoreDebug DAUTHCTRL: UIDAPEN, Mask

◆ CoreDebug_DAUTHCTRL_UIDAPEN_Msk [3/3]

#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk   (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos)
Deprecated
CoreDebug DAUTHCTRL: UIDAPEN, Mask

◆ CoreDebug_DAUTHCTRL_UIDAPEN_Pos [1/3]

#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos   9U
Deprecated
CoreDebug DAUTHCTRL: UIDAPEN, Position
Deprecated
CoreDebug DAUTHCTRL: UIDAPEN, Position
Deprecated
CoreDebug DAUTHCTRL: UIDAPEN, Position

◆ CoreDebug_DAUTHCTRL_UIDAPEN_Pos [2/3]

#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos   9U
Deprecated
CoreDebug DAUTHCTRL: UIDAPEN, Position
Deprecated
CoreDebug DAUTHCTRL: UIDAPEN, Position

◆ CoreDebug_DAUTHCTRL_UIDAPEN_Pos [3/3]

#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos   9U
Deprecated
CoreDebug DAUTHCTRL: UIDAPEN, Position

◆ CoreDebug_DAUTHCTRL_UIDEN_Msk [1/3]

#define CoreDebug_DAUTHCTRL_UIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos)
Deprecated
CoreDebug DAUTHCTRL: UIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: UIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: UIDEN, Mask

◆ CoreDebug_DAUTHCTRL_UIDEN_Msk [2/3]

#define CoreDebug_DAUTHCTRL_UIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos)
Deprecated
CoreDebug DAUTHCTRL: UIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: UIDEN, Mask

◆ CoreDebug_DAUTHCTRL_UIDEN_Msk [3/3]

#define CoreDebug_DAUTHCTRL_UIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos)
Deprecated
CoreDebug DAUTHCTRL: UIDEN, Mask

◆ CoreDebug_DAUTHCTRL_UIDEN_Pos [1/3]

#define CoreDebug_DAUTHCTRL_UIDEN_Pos   10U
Deprecated
CoreDebug DAUTHCTRL: UIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: UIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: UIDEN, Position

◆ CoreDebug_DAUTHCTRL_UIDEN_Pos [2/3]

#define CoreDebug_DAUTHCTRL_UIDEN_Pos   10U
Deprecated
CoreDebug DAUTHCTRL: UIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: UIDEN, Position

◆ CoreDebug_DAUTHCTRL_UIDEN_Pos [3/3]

#define CoreDebug_DAUTHCTRL_UIDEN_Pos   10U
Deprecated
CoreDebug DAUTHCTRL: UIDEN, Position

◆ CoreDebug_DHCSR_C_PMOV_Msk [1/3]

#define CoreDebug_DHCSR_C_PMOV_Msk   (1UL << CoreDebug_DHCSR_C_PMOV_Pos)
Deprecated
CoreDebug DHCSR: C_PMOV Mask
Deprecated
CoreDebug DHCSR: C_PMOV Mask
Deprecated
CoreDebug DHCSR: C_PMOV Mask

◆ CoreDebug_DHCSR_C_PMOV_Msk [2/3]

#define CoreDebug_DHCSR_C_PMOV_Msk   (1UL << CoreDebug_DHCSR_C_PMOV_Pos)
Deprecated
CoreDebug DHCSR: C_PMOV Mask
Deprecated
CoreDebug DHCSR: C_PMOV Mask

◆ CoreDebug_DHCSR_C_PMOV_Msk [3/3]

#define CoreDebug_DHCSR_C_PMOV_Msk   (1UL << CoreDebug_DHCSR_C_PMOV_Pos)
Deprecated
CoreDebug DHCSR: C_PMOV Mask

◆ CoreDebug_DHCSR_C_PMOV_Pos [1/3]

#define CoreDebug_DHCSR_C_PMOV_Pos   6U
Deprecated
CoreDebug DHCSR: C_PMOV Position
Deprecated
CoreDebug DHCSR: C_PMOV Position
Deprecated
CoreDebug DHCSR: C_PMOV Position

◆ CoreDebug_DHCSR_C_PMOV_Pos [2/3]

#define CoreDebug_DHCSR_C_PMOV_Pos   6U
Deprecated
CoreDebug DHCSR: C_PMOV Position
Deprecated
CoreDebug DHCSR: C_PMOV Position

◆ CoreDebug_DHCSR_C_PMOV_Pos [3/3]

#define CoreDebug_DHCSR_C_PMOV_Pos   6U
Deprecated
CoreDebug DHCSR: C_PMOV Position

◆ CoreDebug_DHCSR_S_FPD_Msk [1/3]

#define CoreDebug_DHCSR_S_FPD_Msk   (1UL << CoreDebug_DHCSR_S_FPD_Pos)
Deprecated
CoreDebug DHCSR: S_FPD Mask
Deprecated
CoreDebug DHCSR: S_FPD Mask
Deprecated
CoreDebug DHCSR: S_FPD Mask

◆ CoreDebug_DHCSR_S_FPD_Msk [2/3]

#define CoreDebug_DHCSR_S_FPD_Msk   (1UL << CoreDebug_DHCSR_S_FPD_Pos)
Deprecated
CoreDebug DHCSR: S_FPD Mask
Deprecated
CoreDebug DHCSR: S_FPD Mask

◆ CoreDebug_DHCSR_S_FPD_Msk [3/3]

#define CoreDebug_DHCSR_S_FPD_Msk   (1UL << CoreDebug_DHCSR_S_FPD_Pos)
Deprecated
CoreDebug DHCSR: S_FPD Mask

◆ CoreDebug_DHCSR_S_FPD_Pos [1/3]

#define CoreDebug_DHCSR_S_FPD_Pos   23U
Deprecated
CoreDebug DHCSR: S_FPD Position
Deprecated
CoreDebug DHCSR: S_FPD Position
Deprecated
CoreDebug DHCSR: S_FPD Position

◆ CoreDebug_DHCSR_S_FPD_Pos [2/3]

#define CoreDebug_DHCSR_S_FPD_Pos   23U
Deprecated
CoreDebug DHCSR: S_FPD Position
Deprecated
CoreDebug DHCSR: S_FPD Position

◆ CoreDebug_DHCSR_S_FPD_Pos [3/3]

#define CoreDebug_DHCSR_S_FPD_Pos   23U
Deprecated
CoreDebug DHCSR: S_FPD Position

◆ CoreDebug_DHCSR_S_NSUIDE_Msk [1/3]

#define CoreDebug_DHCSR_S_NSUIDE_Msk   (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos)
Deprecated
CoreDebug DHCSR: S_NSUIDE Mask
Deprecated
CoreDebug DHCSR: S_NSUIDE Mask
Deprecated
CoreDebug DHCSR: S_NSUIDE Mask

◆ CoreDebug_DHCSR_S_NSUIDE_Msk [2/3]

#define CoreDebug_DHCSR_S_NSUIDE_Msk   (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos)
Deprecated
CoreDebug DHCSR: S_NSUIDE Mask
Deprecated
CoreDebug DHCSR: S_NSUIDE Mask

◆ CoreDebug_DHCSR_S_NSUIDE_Msk [3/3]

#define CoreDebug_DHCSR_S_NSUIDE_Msk   (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos)
Deprecated
CoreDebug DHCSR: S_NSUIDE Mask

◆ CoreDebug_DHCSR_S_NSUIDE_Pos [1/3]

#define CoreDebug_DHCSR_S_NSUIDE_Pos   21U
Deprecated
CoreDebug DHCSR: S_NSUIDE Position
Deprecated
CoreDebug DHCSR: S_NSUIDE Position
Deprecated
CoreDebug DHCSR: S_NSUIDE Position

◆ CoreDebug_DHCSR_S_NSUIDE_Pos [2/3]

#define CoreDebug_DHCSR_S_NSUIDE_Pos   21U
Deprecated
CoreDebug DHCSR: S_NSUIDE Position
Deprecated
CoreDebug DHCSR: S_NSUIDE Position

◆ CoreDebug_DHCSR_S_NSUIDE_Pos [3/3]

#define CoreDebug_DHCSR_S_NSUIDE_Pos   21U
Deprecated
CoreDebug DHCSR: S_NSUIDE Position

◆ CoreDebug_DHCSR_S_RESTART_ST_Msk [1/8]

#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask

◆ CoreDebug_DHCSR_S_RESTART_ST_Msk [2/8]

#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask

◆ CoreDebug_DHCSR_S_RESTART_ST_Msk [3/8]

#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask

◆ CoreDebug_DHCSR_S_RESTART_ST_Msk [4/8]

#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask

◆ CoreDebug_DHCSR_S_RESTART_ST_Msk [5/8]

#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask

◆ CoreDebug_DHCSR_S_RESTART_ST_Msk [6/8]

#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask

◆ CoreDebug_DHCSR_S_RESTART_ST_Msk [7/8]

#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask

◆ CoreDebug_DHCSR_S_RESTART_ST_Msk [8/8]

#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask

◆ CoreDebug_DHCSR_S_RESTART_ST_Pos [1/8]

#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position

◆ CoreDebug_DHCSR_S_RESTART_ST_Pos [2/8]

#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position

◆ CoreDebug_DHCSR_S_RESTART_ST_Pos [3/8]

#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position

◆ CoreDebug_DHCSR_S_RESTART_ST_Pos [4/8]

#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position

◆ CoreDebug_DHCSR_S_RESTART_ST_Pos [5/8]

#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position

◆ CoreDebug_DHCSR_S_RESTART_ST_Pos [6/8]

#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position

◆ CoreDebug_DHCSR_S_RESTART_ST_Pos [7/8]

#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position

◆ CoreDebug_DHCSR_S_RESTART_ST_Pos [8/8]

#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position

◆ CoreDebug_DHCSR_S_SDE_Msk [1/3]

#define CoreDebug_DHCSR_S_SDE_Msk   (1UL << CoreDebug_DHCSR_S_SDE_Pos)
Deprecated
CoreDebug DHCSR: S_SDE Mask
Deprecated
CoreDebug DHCSR: S_SDE Mask
Deprecated
CoreDebug DHCSR: S_SDE Mask

◆ CoreDebug_DHCSR_S_SDE_Msk [2/3]

#define CoreDebug_DHCSR_S_SDE_Msk   (1UL << CoreDebug_DHCSR_S_SDE_Pos)
Deprecated
CoreDebug DHCSR: S_SDE Mask
Deprecated
CoreDebug DHCSR: S_SDE Mask

◆ CoreDebug_DHCSR_S_SDE_Msk [3/3]

#define CoreDebug_DHCSR_S_SDE_Msk   (1UL << CoreDebug_DHCSR_S_SDE_Pos)
Deprecated
CoreDebug DHCSR: S_SDE Mask

◆ CoreDebug_DHCSR_S_SDE_Pos [1/3]

#define CoreDebug_DHCSR_S_SDE_Pos   20U
Deprecated
CoreDebug DHCSR: S_SDE Position
Deprecated
CoreDebug DHCSR: S_SDE Position
Deprecated
CoreDebug DHCSR: S_SDE Position

◆ CoreDebug_DHCSR_S_SDE_Pos [2/3]

#define CoreDebug_DHCSR_S_SDE_Pos   20U
Deprecated
CoreDebug DHCSR: S_SDE Position
Deprecated
CoreDebug DHCSR: S_SDE Position

◆ CoreDebug_DHCSR_S_SDE_Pos [3/3]

#define CoreDebug_DHCSR_S_SDE_Pos   20U
Deprecated
CoreDebug DHCSR: S_SDE Position

◆ CoreDebug_DHCSR_S_SUIDE_Msk [1/3]

#define CoreDebug_DHCSR_S_SUIDE_Msk   (1UL << CoreDebug_DHCSR_S_SUIDE_Pos)
Deprecated
CoreDebug DHCSR: S_SUIDE Mask
Deprecated
CoreDebug DHCSR: S_SUIDE Mask
Deprecated
CoreDebug DHCSR: S_SUIDE Mask

◆ CoreDebug_DHCSR_S_SUIDE_Msk [2/3]

#define CoreDebug_DHCSR_S_SUIDE_Msk   (1UL << CoreDebug_DHCSR_S_SUIDE_Pos)
Deprecated
CoreDebug DHCSR: S_SUIDE Mask
Deprecated
CoreDebug DHCSR: S_SUIDE Mask

◆ CoreDebug_DHCSR_S_SUIDE_Msk [3/3]

#define CoreDebug_DHCSR_S_SUIDE_Msk   (1UL << CoreDebug_DHCSR_S_SUIDE_Pos)
Deprecated
CoreDebug DHCSR: S_SUIDE Mask

◆ CoreDebug_DHCSR_S_SUIDE_Pos [1/3]

#define CoreDebug_DHCSR_S_SUIDE_Pos   22U
Deprecated
CoreDebug DHCSR: S_SUIDE Position
Deprecated
CoreDebug DHCSR: S_SUIDE Position
Deprecated
CoreDebug DHCSR: S_SUIDE Position

◆ CoreDebug_DHCSR_S_SUIDE_Pos [2/3]

#define CoreDebug_DHCSR_S_SUIDE_Pos   22U
Deprecated
CoreDebug DHCSR: S_SUIDE Position
Deprecated
CoreDebug DHCSR: S_SUIDE Position

◆ CoreDebug_DHCSR_S_SUIDE_Pos [3/3]

#define CoreDebug_DHCSR_S_SUIDE_Pos   22U
Deprecated
CoreDebug DHCSR: S_SUIDE Position

◆ CoreDebug_DSCEMCR_CLR_MON_PEND_Msk [1/3]

#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk   (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos)
Deprecated
CoreDebug DSCEMCR: CLR_MON_PEND, Mask
Deprecated
CoreDebug DSCEMCR: CLR_MON_PEND, Mask
Deprecated
CoreDebug DSCEMCR: CLR_MON_PEND, Mask

◆ CoreDebug_DSCEMCR_CLR_MON_PEND_Msk [2/3]

#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk   (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos)
Deprecated
CoreDebug DSCEMCR: CLR_MON_PEND, Mask
Deprecated
CoreDebug DSCEMCR: CLR_MON_PEND, Mask

◆ CoreDebug_DSCEMCR_CLR_MON_PEND_Msk [3/3]

#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk   (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos)
Deprecated
CoreDebug DSCEMCR: CLR_MON_PEND, Mask

◆ CoreDebug_DSCEMCR_CLR_MON_PEND_Pos [1/3]

#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos   17U
Deprecated
CoreDebug DSCEMCR: CLR_MON_PEND, Position
Deprecated
CoreDebug DSCEMCR: CLR_MON_PEND, Position
Deprecated
CoreDebug DSCEMCR: CLR_MON_PEND, Position

◆ CoreDebug_DSCEMCR_CLR_MON_PEND_Pos [2/3]

#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos   17U
Deprecated
CoreDebug DSCEMCR: CLR_MON_PEND, Position
Deprecated
CoreDebug DSCEMCR: CLR_MON_PEND, Position

◆ CoreDebug_DSCEMCR_CLR_MON_PEND_Pos [3/3]

#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos   17U
Deprecated
CoreDebug DSCEMCR: CLR_MON_PEND, Position

◆ CoreDebug_DSCEMCR_CLR_MON_REQ_Msk [1/3]

#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk   (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos)
Deprecated
CoreDebug DSCEMCR: CLR_MON_REQ, Mask
Deprecated
CoreDebug DSCEMCR: CLR_MON_REQ, Mask
Deprecated
CoreDebug DSCEMCR: CLR_MON_REQ, Mask

◆ CoreDebug_DSCEMCR_CLR_MON_REQ_Msk [2/3]

#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk   (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos)
Deprecated
CoreDebug DSCEMCR: CLR_MON_REQ, Mask
Deprecated
CoreDebug DSCEMCR: CLR_MON_REQ, Mask

◆ CoreDebug_DSCEMCR_CLR_MON_REQ_Msk [3/3]

#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk   (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos)
Deprecated
CoreDebug DSCEMCR: CLR_MON_REQ, Mask

◆ CoreDebug_DSCEMCR_CLR_MON_REQ_Pos [1/3]

#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos   19U
Deprecated
CoreDebug DSCEMCR: CLR_MON_REQ, Position
Deprecated
CoreDebug DSCEMCR: CLR_MON_REQ, Position
Deprecated
CoreDebug DSCEMCR: CLR_MON_REQ, Position

◆ CoreDebug_DSCEMCR_CLR_MON_REQ_Pos [2/3]

#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos   19U
Deprecated
CoreDebug DSCEMCR: CLR_MON_REQ, Position
Deprecated
CoreDebug DSCEMCR: CLR_MON_REQ, Position

◆ CoreDebug_DSCEMCR_CLR_MON_REQ_Pos [3/3]

#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos   19U
Deprecated
CoreDebug DSCEMCR: CLR_MON_REQ, Position

◆ CoreDebug_DSCEMCR_SET_MON_PEND_Msk [1/3]

#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk   (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos)
Deprecated
CoreDebug DSCEMCR: SET_MON_PEND, Mask
Deprecated
CoreDebug DSCEMCR: SET_MON_PEND, Mask
Deprecated
CoreDebug DSCEMCR: SET_MON_PEND, Mask

◆ CoreDebug_DSCEMCR_SET_MON_PEND_Msk [2/3]

#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk   (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos)
Deprecated
CoreDebug DSCEMCR: SET_MON_PEND, Mask
Deprecated
CoreDebug DSCEMCR: SET_MON_PEND, Mask

◆ CoreDebug_DSCEMCR_SET_MON_PEND_Msk [3/3]

#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk   (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos)
Deprecated
CoreDebug DSCEMCR: SET_MON_PEND, Mask

◆ CoreDebug_DSCEMCR_SET_MON_PEND_Pos [1/3]

#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos   1U
Deprecated
CoreDebug DSCEMCR: SET_MON_PEND, Position
Deprecated
CoreDebug DSCEMCR: SET_MON_PEND, Position
Deprecated
CoreDebug DSCEMCR: SET_MON_PEND, Position

◆ CoreDebug_DSCEMCR_SET_MON_PEND_Pos [2/3]

#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos   1U
Deprecated
CoreDebug DSCEMCR: SET_MON_PEND, Position
Deprecated
CoreDebug DSCEMCR: SET_MON_PEND, Position

◆ CoreDebug_DSCEMCR_SET_MON_PEND_Pos [3/3]

#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos   1U
Deprecated
CoreDebug DSCEMCR: SET_MON_PEND, Position

◆ CoreDebug_DSCEMCR_SET_MON_REQ_Msk [1/3]

#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk   (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos)
Deprecated
CoreDebug DSCEMCR: SET_MON_REQ, Mask
Deprecated
CoreDebug DSCEMCR: SET_MON_REQ, Mask
Deprecated
CoreDebug DSCEMCR: SET_MON_REQ, Mask

◆ CoreDebug_DSCEMCR_SET_MON_REQ_Msk [2/3]

#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk   (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos)
Deprecated
CoreDebug DSCEMCR: SET_MON_REQ, Mask
Deprecated
CoreDebug DSCEMCR: SET_MON_REQ, Mask

◆ CoreDebug_DSCEMCR_SET_MON_REQ_Msk [3/3]

#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk   (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos)
Deprecated
CoreDebug DSCEMCR: SET_MON_REQ, Mask

◆ CoreDebug_DSCEMCR_SET_MON_REQ_Pos [1/3]

#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos   3U
Deprecated
CoreDebug DSCEMCR: SET_MON_REQ, Position
Deprecated
CoreDebug DSCEMCR: SET_MON_REQ, Position
Deprecated
CoreDebug DSCEMCR: SET_MON_REQ, Position

◆ CoreDebug_DSCEMCR_SET_MON_REQ_Pos [2/3]

#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos   3U
Deprecated
CoreDebug DSCEMCR: SET_MON_REQ, Position
Deprecated
CoreDebug DSCEMCR: SET_MON_REQ, Position

◆ CoreDebug_DSCEMCR_SET_MON_REQ_Pos [3/3]

#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos   3U
Deprecated
CoreDebug DSCEMCR: SET_MON_REQ, Position

◆ CoreDebug_DSCSR_CDS_Msk [1/8]

#define CoreDebug_DSCSR_CDS_Msk   (1UL << CoreDebug_DSCSR_CDS_Pos)
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask

◆ CoreDebug_DSCSR_CDS_Msk [2/8]

#define CoreDebug_DSCSR_CDS_Msk   (1UL << CoreDebug_DSCSR_CDS_Pos)
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask

◆ CoreDebug_DSCSR_CDS_Msk [3/8]

#define CoreDebug_DSCSR_CDS_Msk   (1UL << CoreDebug_DSCSR_CDS_Pos)
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask

◆ CoreDebug_DSCSR_CDS_Msk [4/8]

#define CoreDebug_DSCSR_CDS_Msk   (1UL << CoreDebug_DSCSR_CDS_Pos)
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask

◆ CoreDebug_DSCSR_CDS_Msk [5/8]

#define CoreDebug_DSCSR_CDS_Msk   (1UL << CoreDebug_DSCSR_CDS_Pos)
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask

◆ CoreDebug_DSCSR_CDS_Msk [6/8]

#define CoreDebug_DSCSR_CDS_Msk   (1UL << CoreDebug_DSCSR_CDS_Pos)
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask

◆ CoreDebug_DSCSR_CDS_Msk [7/8]

#define CoreDebug_DSCSR_CDS_Msk   (1UL << CoreDebug_DSCSR_CDS_Pos)
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask

◆ CoreDebug_DSCSR_CDS_Msk [8/8]

#define CoreDebug_DSCSR_CDS_Msk   (1UL << CoreDebug_DSCSR_CDS_Pos)
Deprecated
CoreDebug DSCSR: CDS Mask

◆ CoreDebug_DSCSR_CDS_Pos [1/8]

#define CoreDebug_DSCSR_CDS_Pos   16U
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position

◆ CoreDebug_DSCSR_CDS_Pos [2/8]

#define CoreDebug_DSCSR_CDS_Pos   16U
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position

◆ CoreDebug_DSCSR_CDS_Pos [3/8]

#define CoreDebug_DSCSR_CDS_Pos   16U
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position

◆ CoreDebug_DSCSR_CDS_Pos [4/8]

#define CoreDebug_DSCSR_CDS_Pos   16U
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position

◆ CoreDebug_DSCSR_CDS_Pos [5/8]

#define CoreDebug_DSCSR_CDS_Pos   16U
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position

◆ CoreDebug_DSCSR_CDS_Pos [6/8]

#define CoreDebug_DSCSR_CDS_Pos   16U
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position

◆ CoreDebug_DSCSR_CDS_Pos [7/8]

#define CoreDebug_DSCSR_CDS_Pos   16U
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position

◆ CoreDebug_DSCSR_CDS_Pos [8/8]

#define CoreDebug_DSCSR_CDS_Pos   16U
Deprecated
CoreDebug DSCSR: CDS Position

◆ CoreDebug_DSCSR_SBRSEL_Msk [1/8]

#define CoreDebug_DSCSR_SBRSEL_Msk   (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask

◆ CoreDebug_DSCSR_SBRSEL_Msk [2/8]

#define CoreDebug_DSCSR_SBRSEL_Msk   (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask

◆ CoreDebug_DSCSR_SBRSEL_Msk [3/8]

#define CoreDebug_DSCSR_SBRSEL_Msk   (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask

◆ CoreDebug_DSCSR_SBRSEL_Msk [4/8]

#define CoreDebug_DSCSR_SBRSEL_Msk   (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask

◆ CoreDebug_DSCSR_SBRSEL_Msk [5/8]

#define CoreDebug_DSCSR_SBRSEL_Msk   (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask

◆ CoreDebug_DSCSR_SBRSEL_Msk [6/8]

#define CoreDebug_DSCSR_SBRSEL_Msk   (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask

◆ CoreDebug_DSCSR_SBRSEL_Msk [7/8]

#define CoreDebug_DSCSR_SBRSEL_Msk   (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask

◆ CoreDebug_DSCSR_SBRSEL_Msk [8/8]

#define CoreDebug_DSCSR_SBRSEL_Msk   (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
Deprecated
CoreDebug DSCSR: SBRSEL Mask

◆ CoreDebug_DSCSR_SBRSEL_Pos [1/8]

#define CoreDebug_DSCSR_SBRSEL_Pos   1U
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position

◆ CoreDebug_DSCSR_SBRSEL_Pos [2/8]

#define CoreDebug_DSCSR_SBRSEL_Pos   1U
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position

◆ CoreDebug_DSCSR_SBRSEL_Pos [3/8]

#define CoreDebug_DSCSR_SBRSEL_Pos   1U
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position

◆ CoreDebug_DSCSR_SBRSEL_Pos [4/8]

#define CoreDebug_DSCSR_SBRSEL_Pos   1U
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position

◆ CoreDebug_DSCSR_SBRSEL_Pos [5/8]

#define CoreDebug_DSCSR_SBRSEL_Pos   1U
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position

◆ CoreDebug_DSCSR_SBRSEL_Pos [6/8]

#define CoreDebug_DSCSR_SBRSEL_Pos   1U
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position

◆ CoreDebug_DSCSR_SBRSEL_Pos [7/8]

#define CoreDebug_DSCSR_SBRSEL_Pos   1U
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position

◆ CoreDebug_DSCSR_SBRSEL_Pos [8/8]

#define CoreDebug_DSCSR_SBRSEL_Pos   1U
Deprecated
CoreDebug DSCSR: SBRSEL Position

◆ CoreDebug_DSCSR_SBRSELEN_Msk [1/8]

#define CoreDebug_DSCSR_SBRSELEN_Msk   (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask

◆ CoreDebug_DSCSR_SBRSELEN_Msk [2/8]

#define CoreDebug_DSCSR_SBRSELEN_Msk   (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask

◆ CoreDebug_DSCSR_SBRSELEN_Msk [3/8]

#define CoreDebug_DSCSR_SBRSELEN_Msk   (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask

◆ CoreDebug_DSCSR_SBRSELEN_Msk [4/8]

#define CoreDebug_DSCSR_SBRSELEN_Msk   (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask

◆ CoreDebug_DSCSR_SBRSELEN_Msk [5/8]

#define CoreDebug_DSCSR_SBRSELEN_Msk   (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask

◆ CoreDebug_DSCSR_SBRSELEN_Msk [6/8]

#define CoreDebug_DSCSR_SBRSELEN_Msk   (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask

◆ CoreDebug_DSCSR_SBRSELEN_Msk [7/8]

#define CoreDebug_DSCSR_SBRSELEN_Msk   (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask

◆ CoreDebug_DSCSR_SBRSELEN_Msk [8/8]

#define CoreDebug_DSCSR_SBRSELEN_Msk   (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
Deprecated
CoreDebug DSCSR: SBRSELEN Mask

◆ CoreDebug_DSCSR_SBRSELEN_Pos [1/8]

#define CoreDebug_DSCSR_SBRSELEN_Pos   0U
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position

◆ CoreDebug_DSCSR_SBRSELEN_Pos [2/8]

#define CoreDebug_DSCSR_SBRSELEN_Pos   0U
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position

◆ CoreDebug_DSCSR_SBRSELEN_Pos [3/8]

#define CoreDebug_DSCSR_SBRSELEN_Pos   0U
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position

◆ CoreDebug_DSCSR_SBRSELEN_Pos [4/8]

#define CoreDebug_DSCSR_SBRSELEN_Pos   0U
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position

◆ CoreDebug_DSCSR_SBRSELEN_Pos [5/8]

#define CoreDebug_DSCSR_SBRSELEN_Pos   0U
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position

◆ CoreDebug_DSCSR_SBRSELEN_Pos [6/8]

#define CoreDebug_DSCSR_SBRSELEN_Pos   0U
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position

◆ CoreDebug_DSCSR_SBRSELEN_Pos [7/8]

#define CoreDebug_DSCSR_SBRSELEN_Pos   0U
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position

◆ CoreDebug_DSCSR_SBRSELEN_Pos [8/8]

#define CoreDebug_DSCSR_SBRSELEN_Pos   0U
Deprecated
CoreDebug DSCSR: SBRSELEN Position

◆ DCB_DAUTHCTRL_FSDMA_Msk [1/3]

#define DCB_DAUTHCTRL_FSDMA_Msk   (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos)

DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask

◆ DCB_DAUTHCTRL_FSDMA_Msk [2/3]

#define DCB_DAUTHCTRL_FSDMA_Msk   (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos)

DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask

◆ DCB_DAUTHCTRL_FSDMA_Msk [3/3]

#define DCB_DAUTHCTRL_FSDMA_Msk   (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos)

DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask

◆ DCB_DAUTHCTRL_FSDMA_Pos [1/3]

#define DCB_DAUTHCTRL_FSDMA_Pos   8U

DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position

◆ DCB_DAUTHCTRL_FSDMA_Pos [2/3]

#define DCB_DAUTHCTRL_FSDMA_Pos   8U

DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position

◆ DCB_DAUTHCTRL_FSDMA_Pos [3/3]

#define DCB_DAUTHCTRL_FSDMA_Pos   8U

DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position

◆ DCB_DAUTHCTRL_UIDAPEN_Msk [1/3]

#define DCB_DAUTHCTRL_UIDAPEN_Msk   (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos)

DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask

◆ DCB_DAUTHCTRL_UIDAPEN_Msk [2/3]

#define DCB_DAUTHCTRL_UIDAPEN_Msk   (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos)

DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask

◆ DCB_DAUTHCTRL_UIDAPEN_Msk [3/3]

#define DCB_DAUTHCTRL_UIDAPEN_Msk   (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos)

DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask

◆ DCB_DAUTHCTRL_UIDAPEN_Pos [1/3]

#define DCB_DAUTHCTRL_UIDAPEN_Pos   9U

DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position

◆ DCB_DAUTHCTRL_UIDAPEN_Pos [2/3]

#define DCB_DAUTHCTRL_UIDAPEN_Pos   9U

DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position

◆ DCB_DAUTHCTRL_UIDAPEN_Pos [3/3]

#define DCB_DAUTHCTRL_UIDAPEN_Pos   9U

DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position

◆ DCB_DAUTHCTRL_UIDEN_Msk [1/3]

#define DCB_DAUTHCTRL_UIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos)

DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask

◆ DCB_DAUTHCTRL_UIDEN_Msk [2/3]

#define DCB_DAUTHCTRL_UIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos)

DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask

◆ DCB_DAUTHCTRL_UIDEN_Msk [3/3]

#define DCB_DAUTHCTRL_UIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos)

DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask

◆ DCB_DAUTHCTRL_UIDEN_Pos [1/3]

#define DCB_DAUTHCTRL_UIDEN_Pos   10U

DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position

◆ DCB_DAUTHCTRL_UIDEN_Pos [2/3]

#define DCB_DAUTHCTRL_UIDEN_Pos   10U

DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position

◆ DCB_DAUTHCTRL_UIDEN_Pos [3/3]

#define DCB_DAUTHCTRL_UIDEN_Pos   10U

DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position

◆ DCB_DHCSR_C_PMOV_Msk [1/3]

#define DCB_DHCSR_C_PMOV_Msk   (0x1UL << DCB_DHCSR_C_PMOV_Pos)

DCB DHCSR: Halt on PMU overflow control Mask

◆ DCB_DHCSR_C_PMOV_Msk [2/3]

#define DCB_DHCSR_C_PMOV_Msk   (0x1UL << DCB_DHCSR_C_PMOV_Pos)

DCB DHCSR: Halt on PMU overflow control Mask

◆ DCB_DHCSR_C_PMOV_Msk [3/3]

#define DCB_DHCSR_C_PMOV_Msk   (0x1UL << DCB_DHCSR_C_PMOV_Pos)

DCB DHCSR: Halt on PMU overflow control Mask

◆ DCB_DHCSR_C_PMOV_Pos [1/3]

#define DCB_DHCSR_C_PMOV_Pos   6U

DCB DHCSR: Halt on PMU overflow control Position

◆ DCB_DHCSR_C_PMOV_Pos [2/3]

#define DCB_DHCSR_C_PMOV_Pos   6U

DCB DHCSR: Halt on PMU overflow control Position

◆ DCB_DHCSR_C_PMOV_Pos [3/3]

#define DCB_DHCSR_C_PMOV_Pos   6U

DCB DHCSR: Halt on PMU overflow control Position

◆ DCB_DHCSR_S_FPD_Msk [1/3]

#define DCB_DHCSR_S_FPD_Msk   (0x1UL << DCB_DHCSR_S_FPD_Pos)

DCB DHCSR: Floating-point registers Debuggable Mask

◆ DCB_DHCSR_S_FPD_Msk [2/3]

#define DCB_DHCSR_S_FPD_Msk   (0x1UL << DCB_DHCSR_S_FPD_Pos)

DCB DHCSR: Floating-point registers Debuggable Mask

◆ DCB_DHCSR_S_FPD_Msk [3/3]

#define DCB_DHCSR_S_FPD_Msk   (0x1UL << DCB_DHCSR_S_FPD_Pos)

DCB DHCSR: Floating-point registers Debuggable Mask

◆ DCB_DHCSR_S_FPD_Pos [1/3]

#define DCB_DHCSR_S_FPD_Pos   23U

DCB DHCSR: Floating-point registers Debuggable Position

◆ DCB_DHCSR_S_FPD_Pos [2/3]

#define DCB_DHCSR_S_FPD_Pos   23U

DCB DHCSR: Floating-point registers Debuggable Position

◆ DCB_DHCSR_S_FPD_Pos [3/3]

#define DCB_DHCSR_S_FPD_Pos   23U

DCB DHCSR: Floating-point registers Debuggable Position

◆ DCB_DHCSR_S_NSUIDE_Msk [1/3]

#define DCB_DHCSR_S_NSUIDE_Msk   (0x1UL << DCB_DHCSR_S_NSUIDE_Pos)

DCB DHCSR: Non-secure unprivileged halting debug enabled Mask

◆ DCB_DHCSR_S_NSUIDE_Msk [2/3]

#define DCB_DHCSR_S_NSUIDE_Msk   (0x1UL << DCB_DHCSR_S_NSUIDE_Pos)

DCB DHCSR: Non-secure unprivileged halting debug enabled Mask

◆ DCB_DHCSR_S_NSUIDE_Msk [3/3]

#define DCB_DHCSR_S_NSUIDE_Msk   (0x1UL << DCB_DHCSR_S_NSUIDE_Pos)

DCB DHCSR: Non-secure unprivileged halting debug enabled Mask

◆ DCB_DHCSR_S_NSUIDE_Pos [1/3]

#define DCB_DHCSR_S_NSUIDE_Pos   21U

DCB DHCSR: Non-secure unprivileged halting debug enabled Position

◆ DCB_DHCSR_S_NSUIDE_Pos [2/3]

#define DCB_DHCSR_S_NSUIDE_Pos   21U

DCB DHCSR: Non-secure unprivileged halting debug enabled Position

◆ DCB_DHCSR_S_NSUIDE_Pos [3/3]

#define DCB_DHCSR_S_NSUIDE_Pos   21U

DCB DHCSR: Non-secure unprivileged halting debug enabled Position

◆ DCB_DHCSR_S_SUIDE_Msk [1/3]

#define DCB_DHCSR_S_SUIDE_Msk   (0x1UL << DCB_DHCSR_S_SUIDE_Pos)

DCB DHCSR: Secure unprivileged halting debug enabled Mask

◆ DCB_DHCSR_S_SUIDE_Msk [2/3]

#define DCB_DHCSR_S_SUIDE_Msk   (0x1UL << DCB_DHCSR_S_SUIDE_Pos)

DCB DHCSR: Secure unprivileged halting debug enabled Mask

◆ DCB_DHCSR_S_SUIDE_Msk [3/3]

#define DCB_DHCSR_S_SUIDE_Msk   (0x1UL << DCB_DHCSR_S_SUIDE_Pos)

DCB DHCSR: Secure unprivileged halting debug enabled Mask

◆ DCB_DHCSR_S_SUIDE_Pos [1/3]

#define DCB_DHCSR_S_SUIDE_Pos   22U

DCB DHCSR: Secure unprivileged halting debug enabled Position

◆ DCB_DHCSR_S_SUIDE_Pos [2/3]

#define DCB_DHCSR_S_SUIDE_Pos   22U

DCB DHCSR: Secure unprivileged halting debug enabled Position

◆ DCB_DHCSR_S_SUIDE_Pos [3/3]

#define DCB_DHCSR_S_SUIDE_Pos   22U

DCB DHCSR: Secure unprivileged halting debug enabled Position

◆ DCB_DSCEMCR_CLR_MON_PEND_Msk [1/3]

#define DCB_DSCEMCR_CLR_MON_PEND_Msk   (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos)

DCB DSCEMCR: Clear monitor pend Mask

◆ DCB_DSCEMCR_CLR_MON_PEND_Msk [2/3]

#define DCB_DSCEMCR_CLR_MON_PEND_Msk   (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos)

DCB DSCEMCR: Clear monitor pend Mask

◆ DCB_DSCEMCR_CLR_MON_PEND_Msk [3/3]

#define DCB_DSCEMCR_CLR_MON_PEND_Msk   (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos)

DCB DSCEMCR: Clear monitor pend Mask

◆ DCB_DSCEMCR_CLR_MON_PEND_Pos [1/3]

#define DCB_DSCEMCR_CLR_MON_PEND_Pos   17U

DCB DSCEMCR: Clear monitor pend Position

◆ DCB_DSCEMCR_CLR_MON_PEND_Pos [2/3]

#define DCB_DSCEMCR_CLR_MON_PEND_Pos   17U

DCB DSCEMCR: Clear monitor pend Position

◆ DCB_DSCEMCR_CLR_MON_PEND_Pos [3/3]

#define DCB_DSCEMCR_CLR_MON_PEND_Pos   17U

DCB DSCEMCR: Clear monitor pend Position

◆ DCB_DSCEMCR_CLR_MON_REQ_Msk [1/3]

#define DCB_DSCEMCR_CLR_MON_REQ_Msk   (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos)

DCB DSCEMCR: Clear monitor request Mask

◆ DCB_DSCEMCR_CLR_MON_REQ_Msk [2/3]

#define DCB_DSCEMCR_CLR_MON_REQ_Msk   (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos)

DCB DSCEMCR: Clear monitor request Mask

◆ DCB_DSCEMCR_CLR_MON_REQ_Msk [3/3]

#define DCB_DSCEMCR_CLR_MON_REQ_Msk   (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos)

DCB DSCEMCR: Clear monitor request Mask

◆ DCB_DSCEMCR_CLR_MON_REQ_Pos [1/3]

#define DCB_DSCEMCR_CLR_MON_REQ_Pos   19U

DCB DSCEMCR: Clear monitor request Position

◆ DCB_DSCEMCR_CLR_MON_REQ_Pos [2/3]

#define DCB_DSCEMCR_CLR_MON_REQ_Pos   19U

DCB DSCEMCR: Clear monitor request Position

◆ DCB_DSCEMCR_CLR_MON_REQ_Pos [3/3]

#define DCB_DSCEMCR_CLR_MON_REQ_Pos   19U

DCB DSCEMCR: Clear monitor request Position

◆ DCB_DSCEMCR_SET_MON_PEND_Msk [1/3]

#define DCB_DSCEMCR_SET_MON_PEND_Msk   (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos)

DCB DSCEMCR: Set monitor pend Mask

◆ DCB_DSCEMCR_SET_MON_PEND_Msk [2/3]

#define DCB_DSCEMCR_SET_MON_PEND_Msk   (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos)

DCB DSCEMCR: Set monitor pend Mask

◆ DCB_DSCEMCR_SET_MON_PEND_Msk [3/3]

#define DCB_DSCEMCR_SET_MON_PEND_Msk   (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos)

DCB DSCEMCR: Set monitor pend Mask

◆ DCB_DSCEMCR_SET_MON_PEND_Pos [1/3]

#define DCB_DSCEMCR_SET_MON_PEND_Pos   1U

DCB DSCEMCR: Set monitor pend Position

◆ DCB_DSCEMCR_SET_MON_PEND_Pos [2/3]

#define DCB_DSCEMCR_SET_MON_PEND_Pos   1U

DCB DSCEMCR: Set monitor pend Position

◆ DCB_DSCEMCR_SET_MON_PEND_Pos [3/3]

#define DCB_DSCEMCR_SET_MON_PEND_Pos   1U

DCB DSCEMCR: Set monitor pend Position

◆ DCB_DSCEMCR_SET_MON_REQ_Msk [1/3]

#define DCB_DSCEMCR_SET_MON_REQ_Msk   (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos)

DCB DSCEMCR: Set monitor request Mask

◆ DCB_DSCEMCR_SET_MON_REQ_Msk [2/3]

#define DCB_DSCEMCR_SET_MON_REQ_Msk   (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos)

DCB DSCEMCR: Set monitor request Mask

◆ DCB_DSCEMCR_SET_MON_REQ_Msk [3/3]

#define DCB_DSCEMCR_SET_MON_REQ_Msk   (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos)

DCB DSCEMCR: Set monitor request Mask

◆ DCB_DSCEMCR_SET_MON_REQ_Pos [1/3]

#define DCB_DSCEMCR_SET_MON_REQ_Pos   3U

DCB DSCEMCR: Set monitor request Position

◆ DCB_DSCEMCR_SET_MON_REQ_Pos [2/3]

#define DCB_DSCEMCR_SET_MON_REQ_Pos   3U

DCB DSCEMCR: Set monitor request Position

◆ DCB_DSCEMCR_SET_MON_REQ_Pos [3/3]

#define DCB_DSCEMCR_SET_MON_REQ_Pos   3U

DCB DSCEMCR: Set monitor request Position

◆ DIB_DAUTHSTATUS_NSUID_Msk [1/3]

#define DIB_DAUTHSTATUS_NSUID_Msk   (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos )

DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask

◆ DIB_DAUTHSTATUS_NSUID_Msk [2/3]

#define DIB_DAUTHSTATUS_NSUID_Msk   (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos )

DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask

◆ DIB_DAUTHSTATUS_NSUID_Msk [3/3]

#define DIB_DAUTHSTATUS_NSUID_Msk   (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos )

DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask

◆ DIB_DAUTHSTATUS_NSUID_Pos [1/3]

#define DIB_DAUTHSTATUS_NSUID_Pos   16U

DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position

◆ DIB_DAUTHSTATUS_NSUID_Pos [2/3]

#define DIB_DAUTHSTATUS_NSUID_Pos   16U

DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position

◆ DIB_DAUTHSTATUS_NSUID_Pos [3/3]

#define DIB_DAUTHSTATUS_NSUID_Pos   16U

DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position

◆ DIB_DAUTHSTATUS_NSUNID_Msk [1/3]

#define DIB_DAUTHSTATUS_NSUNID_Msk   (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos )

DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask

◆ DIB_DAUTHSTATUS_NSUNID_Msk [2/3]

#define DIB_DAUTHSTATUS_NSUNID_Msk   (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos )

DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask

◆ DIB_DAUTHSTATUS_NSUNID_Msk [3/3]

#define DIB_DAUTHSTATUS_NSUNID_Msk   (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos )

DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask

◆ DIB_DAUTHSTATUS_NSUNID_Pos [1/3]

#define DIB_DAUTHSTATUS_NSUNID_Pos   18U

DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position

◆ DIB_DAUTHSTATUS_NSUNID_Pos [2/3]

#define DIB_DAUTHSTATUS_NSUNID_Pos   18U

DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position

◆ DIB_DAUTHSTATUS_NSUNID_Pos [3/3]

#define DIB_DAUTHSTATUS_NSUNID_Pos   18U

DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position

◆ DIB_DAUTHSTATUS_SUID_Msk [1/3]

#define DIB_DAUTHSTATUS_SUID_Msk   (0x3UL << DIB_DAUTHSTATUS_SUID_Pos )

DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask

◆ DIB_DAUTHSTATUS_SUID_Msk [2/3]

#define DIB_DAUTHSTATUS_SUID_Msk   (0x3UL << DIB_DAUTHSTATUS_SUID_Pos )

DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask

◆ DIB_DAUTHSTATUS_SUID_Msk [3/3]

#define DIB_DAUTHSTATUS_SUID_Msk   (0x3UL << DIB_DAUTHSTATUS_SUID_Pos )

DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask

◆ DIB_DAUTHSTATUS_SUID_Pos [1/3]

#define DIB_DAUTHSTATUS_SUID_Pos   20U

DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position

◆ DIB_DAUTHSTATUS_SUID_Pos [2/3]

#define DIB_DAUTHSTATUS_SUID_Pos   20U

DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position

◆ DIB_DAUTHSTATUS_SUID_Pos [3/3]

#define DIB_DAUTHSTATUS_SUID_Pos   20U

DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position

◆ DIB_DAUTHSTATUS_SUNID_Msk [1/3]

#define DIB_DAUTHSTATUS_SUNID_Msk   (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos )

DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask

◆ DIB_DAUTHSTATUS_SUNID_Msk [2/3]

#define DIB_DAUTHSTATUS_SUNID_Msk   (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos )

DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask

◆ DIB_DAUTHSTATUS_SUNID_Msk [3/3]

#define DIB_DAUTHSTATUS_SUNID_Msk   (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos )

DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask

◆ DIB_DAUTHSTATUS_SUNID_Pos [1/3]

#define DIB_DAUTHSTATUS_SUNID_Pos   22U

DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position

◆ DIB_DAUTHSTATUS_SUNID_Pos [2/3]

#define DIB_DAUTHSTATUS_SUNID_Pos   22U

DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position

◆ DIB_DAUTHSTATUS_SUNID_Pos [3/3]

#define DIB_DAUTHSTATUS_SUNID_Pos   22U

DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position

◆ ERRBNK [1/2]

#define ERRBNK   ((ErrBnk_Type *) ERRBNK_BASE )

Error Banking configuration struct

◆ ERRBNK [2/2]

#define ERRBNK   ((ErrBnk_Type *) ERRBNK_BASE )

Error Banking configuration struct

◆ ERRBNK_BASE [1/2]

#define ERRBNK_BASE   (0xE001E100UL)

Error Banking Base Address

◆ ERRBNK_BASE [2/2]

#define ERRBNK_BASE   (0xE001E100UL)

Error Banking Base Address

◆ ERRBNK_DEBR0_BANK_Msk [1/2]

#define ERRBNK_DEBR0_BANK_Msk   (0x1UL << ERRBNK_DEBR0_BANK_Pos)

ERRBNK DEBR0: BANK Mask

◆ ERRBNK_DEBR0_BANK_Msk [2/2]

#define ERRBNK_DEBR0_BANK_Msk   (0x1UL << ERRBNK_DEBR0_BANK_Pos)

ERRBNK DEBR0: BANK Mask

◆ ERRBNK_DEBR0_BANK_Pos [1/2]

#define ERRBNK_DEBR0_BANK_Pos   16U

ERRBNK DEBR0: BANK Position

◆ ERRBNK_DEBR0_BANK_Pos [2/2]

#define ERRBNK_DEBR0_BANK_Pos   16U

ERRBNK DEBR0: BANK Position

◆ ERRBNK_DEBR0_LOCATION_Msk [1/2]

#define ERRBNK_DEBR0_LOCATION_Msk   (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos)

ERRBNK DEBR0: LOCATION Mask

◆ ERRBNK_DEBR0_LOCATION_Msk [2/2]

#define ERRBNK_DEBR0_LOCATION_Msk   (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos)

ERRBNK DEBR0: LOCATION Mask

◆ ERRBNK_DEBR0_LOCATION_Pos [1/2]

#define ERRBNK_DEBR0_LOCATION_Pos   2U

ERRBNK DEBR0: LOCATION Position

◆ ERRBNK_DEBR0_LOCATION_Pos [2/2]

#define ERRBNK_DEBR0_LOCATION_Pos   2U

ERRBNK DEBR0: LOCATION Position

◆ ERRBNK_DEBR0_LOCKED_Msk [1/2]

#define ERRBNK_DEBR0_LOCKED_Msk   (0x1UL << ERRBNK_DEBR0_LOCKED_Pos)

ERRBNK DEBR0: LOCKED Mask

◆ ERRBNK_DEBR0_LOCKED_Msk [2/2]

#define ERRBNK_DEBR0_LOCKED_Msk   (0x1UL << ERRBNK_DEBR0_LOCKED_Pos)

ERRBNK DEBR0: LOCKED Mask

◆ ERRBNK_DEBR0_LOCKED_Pos [1/2]

#define ERRBNK_DEBR0_LOCKED_Pos   1U

ERRBNK DEBR0: LOCKED Position

◆ ERRBNK_DEBR0_LOCKED_Pos [2/2]

#define ERRBNK_DEBR0_LOCKED_Pos   1U

ERRBNK DEBR0: LOCKED Position

◆ ERRBNK_DEBR0_SWDEF_Msk [1/2]

#define ERRBNK_DEBR0_SWDEF_Msk   (0x3UL << ERRBNK_DEBR0_SWDEF_Pos)

ERRBNK DEBR0: SWDEF Mask

◆ ERRBNK_DEBR0_SWDEF_Msk [2/2]

#define ERRBNK_DEBR0_SWDEF_Msk   (0x3UL << ERRBNK_DEBR0_SWDEF_Pos)

ERRBNK DEBR0: SWDEF Mask

◆ ERRBNK_DEBR0_SWDEF_Pos [1/2]

#define ERRBNK_DEBR0_SWDEF_Pos   30U

ERRBNK DEBR0: SWDEF Position

◆ ERRBNK_DEBR0_SWDEF_Pos [2/2]

#define ERRBNK_DEBR0_SWDEF_Pos   30U

ERRBNK DEBR0: SWDEF Position

◆ ERRBNK_DEBR0_TYPE_Msk [1/2]

#define ERRBNK_DEBR0_TYPE_Msk   (0x1UL << ERRBNK_DEBR0_TYPE_Pos)

ERRBNK DEBR0: TYPE Mask

◆ ERRBNK_DEBR0_TYPE_Msk [2/2]

#define ERRBNK_DEBR0_TYPE_Msk   (0x1UL << ERRBNK_DEBR0_TYPE_Pos)

ERRBNK DEBR0: TYPE Mask

◆ ERRBNK_DEBR0_TYPE_Pos [1/2]

#define ERRBNK_DEBR0_TYPE_Pos   17U

ERRBNK DEBR0: TYPE Position

◆ ERRBNK_DEBR0_TYPE_Pos [2/2]

#define ERRBNK_DEBR0_TYPE_Pos   17U

ERRBNK DEBR0: TYPE Position

◆ ERRBNK_DEBR0_VALID_Msk [1/2]

#define ERRBNK_DEBR0_VALID_Msk   (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/)

ERRBNK DEBR0: VALID Mask

◆ ERRBNK_DEBR0_VALID_Msk [2/2]

#define ERRBNK_DEBR0_VALID_Msk   (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/)

ERRBNK DEBR0: VALID Mask

◆ ERRBNK_DEBR0_VALID_Pos [1/2]

#define ERRBNK_DEBR0_VALID_Pos   0U

ERRBNK DEBR0: VALID Position

◆ ERRBNK_DEBR0_VALID_Pos [2/2]

#define ERRBNK_DEBR0_VALID_Pos   0U

ERRBNK DEBR0: VALID Position

◆ ERRBNK_DEBR1_BANK_Msk [1/2]

#define ERRBNK_DEBR1_BANK_Msk   (0x1UL << ERRBNK_DEBR1_BANK_Pos)

ERRBNK DEBR1: BANK Mask

◆ ERRBNK_DEBR1_BANK_Msk [2/2]

#define ERRBNK_DEBR1_BANK_Msk   (0x1UL << ERRBNK_DEBR1_BANK_Pos)

ERRBNK DEBR1: BANK Mask

◆ ERRBNK_DEBR1_BANK_Pos [1/2]

#define ERRBNK_DEBR1_BANK_Pos   16U

ERRBNK DEBR1: BANK Position

◆ ERRBNK_DEBR1_BANK_Pos [2/2]

#define ERRBNK_DEBR1_BANK_Pos   16U

ERRBNK DEBR1: BANK Position

◆ ERRBNK_DEBR1_LOCATION_Msk [1/2]

#define ERRBNK_DEBR1_LOCATION_Msk   (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos)

ERRBNK DEBR1: LOCATION Mask

◆ ERRBNK_DEBR1_LOCATION_Msk [2/2]

#define ERRBNK_DEBR1_LOCATION_Msk   (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos)

ERRBNK DEBR1: LOCATION Mask

◆ ERRBNK_DEBR1_LOCATION_Pos [1/2]

#define ERRBNK_DEBR1_LOCATION_Pos   2U

ERRBNK DEBR1: LOCATION Position

◆ ERRBNK_DEBR1_LOCATION_Pos [2/2]

#define ERRBNK_DEBR1_LOCATION_Pos   2U

ERRBNK DEBR1: LOCATION Position

◆ ERRBNK_DEBR1_LOCKED_Msk [1/2]

#define ERRBNK_DEBR1_LOCKED_Msk   (0x1UL << ERRBNK_DEBR1_LOCKED_Pos)

ERRBNK DEBR1: LOCKED Mask

◆ ERRBNK_DEBR1_LOCKED_Msk [2/2]

#define ERRBNK_DEBR1_LOCKED_Msk   (0x1UL << ERRBNK_DEBR1_LOCKED_Pos)

ERRBNK DEBR1: LOCKED Mask

◆ ERRBNK_DEBR1_LOCKED_Pos [1/2]

#define ERRBNK_DEBR1_LOCKED_Pos   1U

ERRBNK DEBR1: LOCKED Position

◆ ERRBNK_DEBR1_LOCKED_Pos [2/2]

#define ERRBNK_DEBR1_LOCKED_Pos   1U

ERRBNK DEBR1: LOCKED Position

◆ ERRBNK_DEBR1_SWDEF_Msk [1/2]

#define ERRBNK_DEBR1_SWDEF_Msk   (0x3UL << ERRBNK_DEBR1_SWDEF_Pos)

ERRBNK DEBR1: SWDEF Mask

◆ ERRBNK_DEBR1_SWDEF_Msk [2/2]

#define ERRBNK_DEBR1_SWDEF_Msk   (0x3UL << ERRBNK_DEBR1_SWDEF_Pos)

ERRBNK DEBR1: SWDEF Mask

◆ ERRBNK_DEBR1_SWDEF_Pos [1/2]

#define ERRBNK_DEBR1_SWDEF_Pos   30U

ERRBNK DEBR1: SWDEF Position

◆ ERRBNK_DEBR1_SWDEF_Pos [2/2]

#define ERRBNK_DEBR1_SWDEF_Pos   30U

ERRBNK DEBR1: SWDEF Position

◆ ERRBNK_DEBR1_TYPE_Msk [1/2]

#define ERRBNK_DEBR1_TYPE_Msk   (0x1UL << ERRBNK_DEBR1_TYPE_Pos)

ERRBNK DEBR1: TYPE Mask

◆ ERRBNK_DEBR1_TYPE_Msk [2/2]

#define ERRBNK_DEBR1_TYPE_Msk   (0x1UL << ERRBNK_DEBR1_TYPE_Pos)

ERRBNK DEBR1: TYPE Mask

◆ ERRBNK_DEBR1_TYPE_Pos [1/2]

#define ERRBNK_DEBR1_TYPE_Pos   17U

ERRBNK DEBR1: TYPE Position

◆ ERRBNK_DEBR1_TYPE_Pos [2/2]

#define ERRBNK_DEBR1_TYPE_Pos   17U

ERRBNK DEBR1: TYPE Position

◆ ERRBNK_DEBR1_VALID_Msk [1/2]

#define ERRBNK_DEBR1_VALID_Msk   (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/)

ERRBNK DEBR1: VALID Mask

◆ ERRBNK_DEBR1_VALID_Msk [2/2]

#define ERRBNK_DEBR1_VALID_Msk   (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/)

ERRBNK DEBR1: VALID Mask

◆ ERRBNK_DEBR1_VALID_Pos [1/2]

#define ERRBNK_DEBR1_VALID_Pos   0U

ERRBNK DEBR1: VALID Position

◆ ERRBNK_DEBR1_VALID_Pos [2/2]

#define ERRBNK_DEBR1_VALID_Pos   0U

ERRBNK DEBR1: VALID Position

◆ ERRBNK_IEBR0_BANK_Msk [1/2]

#define ERRBNK_IEBR0_BANK_Msk   (0x1UL << ERRBNK_IEBR0_BANK_Pos)

ERRBNK IEBR0: BANK Mask

◆ ERRBNK_IEBR0_BANK_Msk [2/2]

#define ERRBNK_IEBR0_BANK_Msk   (0x1UL << ERRBNK_IEBR0_BANK_Pos)

ERRBNK IEBR0: BANK Mask

◆ ERRBNK_IEBR0_BANK_Pos [1/2]

#define ERRBNK_IEBR0_BANK_Pos   16U

ERRBNK IEBR0: BANK Position

◆ ERRBNK_IEBR0_BANK_Pos [2/2]

#define ERRBNK_IEBR0_BANK_Pos   16U

ERRBNK IEBR0: BANK Position

◆ ERRBNK_IEBR0_LOCATION_Msk [1/2]

#define ERRBNK_IEBR0_LOCATION_Msk   (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos)

ERRBNK IEBR0: LOCATION Mask

◆ ERRBNK_IEBR0_LOCATION_Msk [2/2]

#define ERRBNK_IEBR0_LOCATION_Msk   (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos)

ERRBNK IEBR0: LOCATION Mask

◆ ERRBNK_IEBR0_LOCATION_Pos [1/2]

#define ERRBNK_IEBR0_LOCATION_Pos   2U

ERRBNK IEBR0: LOCATION Position

◆ ERRBNK_IEBR0_LOCATION_Pos [2/2]

#define ERRBNK_IEBR0_LOCATION_Pos   2U

ERRBNK IEBR0: LOCATION Position

◆ ERRBNK_IEBR0_LOCKED_Msk [1/2]

#define ERRBNK_IEBR0_LOCKED_Msk   (0x1UL << ERRBNK_IEBR0_LOCKED_Pos)

ERRBNK IEBR0: LOCKED Mask

◆ ERRBNK_IEBR0_LOCKED_Msk [2/2]

#define ERRBNK_IEBR0_LOCKED_Msk   (0x1UL << ERRBNK_IEBR0_LOCKED_Pos)

ERRBNK IEBR0: LOCKED Mask

◆ ERRBNK_IEBR0_LOCKED_Pos [1/2]

#define ERRBNK_IEBR0_LOCKED_Pos   1U

ERRBNK IEBR0: LOCKED Position

◆ ERRBNK_IEBR0_LOCKED_Pos [2/2]

#define ERRBNK_IEBR0_LOCKED_Pos   1U

ERRBNK IEBR0: LOCKED Position

◆ ERRBNK_IEBR0_SWDEF_Msk [1/2]

#define ERRBNK_IEBR0_SWDEF_Msk   (0x3UL << ERRBNK_IEBR0_SWDEF_Pos)

ERRBNK IEBR0: SWDEF Mask

◆ ERRBNK_IEBR0_SWDEF_Msk [2/2]

#define ERRBNK_IEBR0_SWDEF_Msk   (0x3UL << ERRBNK_IEBR0_SWDEF_Pos)

ERRBNK IEBR0: SWDEF Mask

◆ ERRBNK_IEBR0_SWDEF_Pos [1/2]

#define ERRBNK_IEBR0_SWDEF_Pos   30U

ERRBNK IEBR0: SWDEF Position

◆ ERRBNK_IEBR0_SWDEF_Pos [2/2]

#define ERRBNK_IEBR0_SWDEF_Pos   30U

ERRBNK IEBR0: SWDEF Position

◆ ERRBNK_IEBR0_VALID_Msk [1/2]

#define ERRBNK_IEBR0_VALID_Msk   (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/)

ERRBNK IEBR0: VALID Mask

◆ ERRBNK_IEBR0_VALID_Msk [2/2]

#define ERRBNK_IEBR0_VALID_Msk   (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/)

ERRBNK IEBR0: VALID Mask

◆ ERRBNK_IEBR0_VALID_Pos [1/2]

#define ERRBNK_IEBR0_VALID_Pos   0U

ERRBNK IEBR0: VALID Position

◆ ERRBNK_IEBR0_VALID_Pos [2/2]

#define ERRBNK_IEBR0_VALID_Pos   0U

ERRBNK IEBR0: VALID Position

◆ ERRBNK_IEBR1_BANK_Msk [1/2]

#define ERRBNK_IEBR1_BANK_Msk   (0x1UL << ERRBNK_IEBR1_BANK_Pos)

ERRBNK IEBR1: BANK Mask

◆ ERRBNK_IEBR1_BANK_Msk [2/2]

#define ERRBNK_IEBR1_BANK_Msk   (0x1UL << ERRBNK_IEBR1_BANK_Pos)

ERRBNK IEBR1: BANK Mask

◆ ERRBNK_IEBR1_BANK_Pos [1/2]

#define ERRBNK_IEBR1_BANK_Pos   16U

ERRBNK IEBR1: BANK Position

◆ ERRBNK_IEBR1_BANK_Pos [2/2]

#define ERRBNK_IEBR1_BANK_Pos   16U

ERRBNK IEBR1: BANK Position

◆ ERRBNK_IEBR1_LOCATION_Msk [1/2]

#define ERRBNK_IEBR1_LOCATION_Msk   (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos)

ERRBNK IEBR1: LOCATION Mask

◆ ERRBNK_IEBR1_LOCATION_Msk [2/2]

#define ERRBNK_IEBR1_LOCATION_Msk   (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos)

ERRBNK IEBR1: LOCATION Mask

◆ ERRBNK_IEBR1_LOCATION_Pos [1/2]

#define ERRBNK_IEBR1_LOCATION_Pos   2U

ERRBNK IEBR1: LOCATION Position

◆ ERRBNK_IEBR1_LOCATION_Pos [2/2]

#define ERRBNK_IEBR1_LOCATION_Pos   2U

ERRBNK IEBR1: LOCATION Position

◆ ERRBNK_IEBR1_LOCKED_Msk [1/2]

#define ERRBNK_IEBR1_LOCKED_Msk   (0x1UL << ERRBNK_IEBR1_LOCKED_Pos)

ERRBNK IEBR1: LOCKED Mask

◆ ERRBNK_IEBR1_LOCKED_Msk [2/2]

#define ERRBNK_IEBR1_LOCKED_Msk   (0x1UL << ERRBNK_IEBR1_LOCKED_Pos)

ERRBNK IEBR1: LOCKED Mask

◆ ERRBNK_IEBR1_LOCKED_Pos [1/2]

#define ERRBNK_IEBR1_LOCKED_Pos   1U

ERRBNK IEBR1: LOCKED Position

◆ ERRBNK_IEBR1_LOCKED_Pos [2/2]

#define ERRBNK_IEBR1_LOCKED_Pos   1U

ERRBNK IEBR1: LOCKED Position

◆ ERRBNK_IEBR1_SWDEF_Msk [1/2]

#define ERRBNK_IEBR1_SWDEF_Msk   (0x3UL << ERRBNK_IEBR1_SWDEF_Pos)

ERRBNK IEBR1: SWDEF Mask

◆ ERRBNK_IEBR1_SWDEF_Msk [2/2]

#define ERRBNK_IEBR1_SWDEF_Msk   (0x3UL << ERRBNK_IEBR1_SWDEF_Pos)

ERRBNK IEBR1: SWDEF Mask

◆ ERRBNK_IEBR1_SWDEF_Pos [1/2]

#define ERRBNK_IEBR1_SWDEF_Pos   30U

ERRBNK IEBR1: SWDEF Position

◆ ERRBNK_IEBR1_SWDEF_Pos [2/2]

#define ERRBNK_IEBR1_SWDEF_Pos   30U

ERRBNK IEBR1: SWDEF Position

◆ ERRBNK_IEBR1_VALID_Msk [1/2]

#define ERRBNK_IEBR1_VALID_Msk   (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/)

ERRBNK IEBR1: VALID Mask

◆ ERRBNK_IEBR1_VALID_Msk [2/2]

#define ERRBNK_IEBR1_VALID_Msk   (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/)

ERRBNK IEBR1: VALID Mask

◆ ERRBNK_IEBR1_VALID_Pos [1/2]

#define ERRBNK_IEBR1_VALID_Pos   0U

ERRBNK IEBR1: VALID Position

◆ ERRBNK_IEBR1_VALID_Pos [2/2]

#define ERRBNK_IEBR1_VALID_Pos   0U

ERRBNK IEBR1: VALID Position

◆ ERRBNK_TEBR0_BANK_Msk [1/2]

#define ERRBNK_TEBR0_BANK_Msk   (0x3UL << ERRBNK_TEBR0_BANK_Pos)

ERRBNK TEBR0: BANK Mask

◆ ERRBNK_TEBR0_BANK_Msk [2/2]

#define ERRBNK_TEBR0_BANK_Msk   (0x3UL << ERRBNK_TEBR0_BANK_Pos)

ERRBNK TEBR0: BANK Mask

◆ ERRBNK_TEBR0_BANK_Pos [1/2]

#define ERRBNK_TEBR0_BANK_Pos   24U

ERRBNK TEBR0: BANK Position

◆ ERRBNK_TEBR0_BANK_Pos [2/2]

#define ERRBNK_TEBR0_BANK_Pos   24U

ERRBNK TEBR0: BANK Position

◆ ERRBNK_TEBR0_LOCATION_Msk [1/2]

#define ERRBNK_TEBR0_LOCATION_Msk   (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos)

ERRBNK TEBR0: LOCATION Mask

◆ ERRBNK_TEBR0_LOCATION_Msk [2/2]

#define ERRBNK_TEBR0_LOCATION_Msk   (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos)

ERRBNK TEBR0: LOCATION Mask

◆ ERRBNK_TEBR0_LOCATION_Pos [1/2]

#define ERRBNK_TEBR0_LOCATION_Pos   2U

ERRBNK TEBR0: LOCATION Position

◆ ERRBNK_TEBR0_LOCATION_Pos [2/2]

#define ERRBNK_TEBR0_LOCATION_Pos   2U

ERRBNK TEBR0: LOCATION Position

◆ ERRBNK_TEBR0_LOCKED_Msk [1/2]

#define ERRBNK_TEBR0_LOCKED_Msk   (0x1UL << ERRBNK_TEBR0_LOCKED_Pos)

ERRBNK TEBR0: LOCKED Mask

◆ ERRBNK_TEBR0_LOCKED_Msk [2/2]

#define ERRBNK_TEBR0_LOCKED_Msk   (0x1UL << ERRBNK_TEBR0_LOCKED_Pos)

ERRBNK TEBR0: LOCKED Mask

◆ ERRBNK_TEBR0_LOCKED_Pos [1/2]

#define ERRBNK_TEBR0_LOCKED_Pos   1U

ERRBNK TEBR0: LOCKED Position

◆ ERRBNK_TEBR0_LOCKED_Pos [2/2]

#define ERRBNK_TEBR0_LOCKED_Pos   1U

ERRBNK TEBR0: LOCKED Position

◆ ERRBNK_TEBR0_POISON_Msk [1/2]

#define ERRBNK_TEBR0_POISON_Msk   (0x1UL << ERRBNK_TEBR0_POISON_Pos)

ERRBNK TEBR0: POISON Mask

◆ ERRBNK_TEBR0_POISON_Msk [2/2]

#define ERRBNK_TEBR0_POISON_Msk   (0x1UL << ERRBNK_TEBR0_POISON_Pos)

ERRBNK TEBR0: POISON Mask

◆ ERRBNK_TEBR0_POISON_Pos [1/2]

#define ERRBNK_TEBR0_POISON_Pos   28U

ERRBNK TEBR0: POISON Position

◆ ERRBNK_TEBR0_POISON_Pos [2/2]

#define ERRBNK_TEBR0_POISON_Pos   28U

ERRBNK TEBR0: POISON Position

◆ ERRBNK_TEBR0_SWDEF_Msk [1/2]

#define ERRBNK_TEBR0_SWDEF_Msk   (0x3UL << ERRBNK_TEBR0_SWDEF_Pos)

ERRBNK TEBR0: SWDEF Mask

◆ ERRBNK_TEBR0_SWDEF_Msk [2/2]

#define ERRBNK_TEBR0_SWDEF_Msk   (0x3UL << ERRBNK_TEBR0_SWDEF_Pos)

ERRBNK TEBR0: SWDEF Mask

◆ ERRBNK_TEBR0_SWDEF_Pos [1/2]

#define ERRBNK_TEBR0_SWDEF_Pos   30U

ERRBNK TEBR0: SWDEF Position

◆ ERRBNK_TEBR0_SWDEF_Pos [2/2]

#define ERRBNK_TEBR0_SWDEF_Pos   30U

ERRBNK TEBR0: SWDEF Position

◆ ERRBNK_TEBR0_TYPE_Msk [1/2]

#define ERRBNK_TEBR0_TYPE_Msk   (0x1UL << ERRBNK_TEBR0_TYPE_Pos)

ERRBNK TEBR0: TYPE Mask

◆ ERRBNK_TEBR0_TYPE_Msk [2/2]

#define ERRBNK_TEBR0_TYPE_Msk   (0x1UL << ERRBNK_TEBR0_TYPE_Pos)

ERRBNK TEBR0: TYPE Mask

◆ ERRBNK_TEBR0_TYPE_Pos [1/2]

#define ERRBNK_TEBR0_TYPE_Pos   27U

ERRBNK TEBR0: TYPE Position

◆ ERRBNK_TEBR0_TYPE_Pos [2/2]

#define ERRBNK_TEBR0_TYPE_Pos   27U

ERRBNK TEBR0: TYPE Position

◆ ERRBNK_TEBR0_VALID_Msk [1/2]

#define ERRBNK_TEBR0_VALID_Msk   (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/)

ERRBNK TEBR0: VALID Mask

◆ ERRBNK_TEBR0_VALID_Msk [2/2]

#define ERRBNK_TEBR0_VALID_Msk   (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/)

ERRBNK TEBR0: VALID Mask

◆ ERRBNK_TEBR0_VALID_Pos [1/2]

#define ERRBNK_TEBR0_VALID_Pos   0U

ERRBNK TEBR0: VALID Position

◆ ERRBNK_TEBR0_VALID_Pos [2/2]

#define ERRBNK_TEBR0_VALID_Pos   0U

ERRBNK TEBR0: VALID Position

◆ ERRBNK_TEBR1_BANK_Msk [1/2]

#define ERRBNK_TEBR1_BANK_Msk   (0x3UL << ERRBNK_TEBR1_BANK_Pos)

ERRBNK TEBR1: BANK Mask

◆ ERRBNK_TEBR1_BANK_Msk [2/2]

#define ERRBNK_TEBR1_BANK_Msk   (0x3UL << ERRBNK_TEBR1_BANK_Pos)

ERRBNK TEBR1: BANK Mask

◆ ERRBNK_TEBR1_BANK_Pos [1/2]

#define ERRBNK_TEBR1_BANK_Pos   24U

ERRBNK TEBR1: BANK Position

◆ ERRBNK_TEBR1_BANK_Pos [2/2]

#define ERRBNK_TEBR1_BANK_Pos   24U

ERRBNK TEBR1: BANK Position

◆ ERRBNK_TEBR1_LOCATION_Msk [1/2]

#define ERRBNK_TEBR1_LOCATION_Msk   (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos)

ERRBNK TEBR1: LOCATION Mask

◆ ERRBNK_TEBR1_LOCATION_Msk [2/2]

#define ERRBNK_TEBR1_LOCATION_Msk   (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos)

ERRBNK TEBR1: LOCATION Mask

◆ ERRBNK_TEBR1_LOCATION_Pos [1/2]

#define ERRBNK_TEBR1_LOCATION_Pos   2U

ERRBNK TEBR1: LOCATION Position

◆ ERRBNK_TEBR1_LOCATION_Pos [2/2]

#define ERRBNK_TEBR1_LOCATION_Pos   2U

ERRBNK TEBR1: LOCATION Position

◆ ERRBNK_TEBR1_LOCKED_Msk [1/2]

#define ERRBNK_TEBR1_LOCKED_Msk   (0x1UL << ERRBNK_TEBR1_LOCKED_Pos)

ERRBNK TEBR1: LOCKED Mask

◆ ERRBNK_TEBR1_LOCKED_Msk [2/2]

#define ERRBNK_TEBR1_LOCKED_Msk   (0x1UL << ERRBNK_TEBR1_LOCKED_Pos)

ERRBNK TEBR1: LOCKED Mask

◆ ERRBNK_TEBR1_LOCKED_Pos [1/2]

#define ERRBNK_TEBR1_LOCKED_Pos   1U

ERRBNK TEBR1: LOCKED Position

◆ ERRBNK_TEBR1_LOCKED_Pos [2/2]

#define ERRBNK_TEBR1_LOCKED_Pos   1U

ERRBNK TEBR1: LOCKED Position

◆ ERRBNK_TEBR1_POISON_Msk [1/2]

#define ERRBNK_TEBR1_POISON_Msk   (0x1UL << ERRBNK_TEBR1_POISON_Pos)

ERRBNK TEBR1: POISON Mask

◆ ERRBNK_TEBR1_POISON_Msk [2/2]

#define ERRBNK_TEBR1_POISON_Msk   (0x1UL << ERRBNK_TEBR1_POISON_Pos)

ERRBNK TEBR1: POISON Mask

◆ ERRBNK_TEBR1_POISON_Pos [1/2]

#define ERRBNK_TEBR1_POISON_Pos   28U

ERRBNK TEBR1: POISON Position

◆ ERRBNK_TEBR1_POISON_Pos [2/2]

#define ERRBNK_TEBR1_POISON_Pos   28U

ERRBNK TEBR1: POISON Position

◆ ERRBNK_TEBR1_SWDEF_Msk [1/2]

#define ERRBNK_TEBR1_SWDEF_Msk   (0x3UL << ERRBNK_TEBR1_SWDEF_Pos)

ERRBNK TEBR1: SWDEF Mask

◆ ERRBNK_TEBR1_SWDEF_Msk [2/2]

#define ERRBNK_TEBR1_SWDEF_Msk   (0x3UL << ERRBNK_TEBR1_SWDEF_Pos)

ERRBNK TEBR1: SWDEF Mask

◆ ERRBNK_TEBR1_SWDEF_Pos [1/2]

#define ERRBNK_TEBR1_SWDEF_Pos   30U

ERRBNK TEBR1: SWDEF Position

◆ ERRBNK_TEBR1_SWDEF_Pos [2/2]

#define ERRBNK_TEBR1_SWDEF_Pos   30U

ERRBNK TEBR1: SWDEF Position

◆ ERRBNK_TEBR1_TYPE_Msk [1/2]

#define ERRBNK_TEBR1_TYPE_Msk   (0x1UL << ERRBNK_TEBR1_TYPE_Pos)

ERRBNK TEBR1: TYPE Mask

◆ ERRBNK_TEBR1_TYPE_Msk [2/2]

#define ERRBNK_TEBR1_TYPE_Msk   (0x1UL << ERRBNK_TEBR1_TYPE_Pos)

ERRBNK TEBR1: TYPE Mask

◆ ERRBNK_TEBR1_TYPE_Pos [1/2]

#define ERRBNK_TEBR1_TYPE_Pos   27U

ERRBNK TEBR1: TYPE Position

◆ ERRBNK_TEBR1_TYPE_Pos [2/2]

#define ERRBNK_TEBR1_TYPE_Pos   27U

ERRBNK TEBR1: TYPE Position

◆ ERRBNK_TEBR1_VALID_Msk [1/2]

#define ERRBNK_TEBR1_VALID_Msk   (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/)

ERRBNK TEBR1: VALID Mask

◆ ERRBNK_TEBR1_VALID_Msk [2/2]

#define ERRBNK_TEBR1_VALID_Msk   (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/)

ERRBNK TEBR1: VALID Mask

◆ ERRBNK_TEBR1_VALID_Pos [1/2]

#define ERRBNK_TEBR1_VALID_Pos   0U

ERRBNK TEBR1: VALID Position

◆ ERRBNK_TEBR1_VALID_Pos [2/2]

#define ERRBNK_TEBR1_VALID_Pos   0U

ERRBNK TEBR1: VALID Position

◆ EWIC [1/2]

#define EWIC   ((EWIC_Type *) EWIC_BASE )

EWIC configuration struct

◆ EWIC [2/2]

#define EWIC   ((EWIC_Type *) EWIC_BASE )

EWIC configuration struct

◆ EWIC_BASE [1/2]

#define EWIC_BASE   (0xE001E400UL)

External Wakeup Interrupt Controller Base Address

◆ EWIC_BASE [2/2]

#define EWIC_BASE   (0xE001E400UL)

External Wakeup Interrupt Controller Base Address

◆ EWIC_EVENTMASK_IRQ_Msk [1/2]

#define EWIC_EVENTMASK_IRQ_Msk   (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/)

EWIC EVENTMASKA: IRQ Mask

◆ EWIC_EVENTMASK_IRQ_Msk [2/2]

#define EWIC_EVENTMASK_IRQ_Msk   (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/)

EWIC EVENTMASKA: IRQ Mask

◆ EWIC_EVENTMASK_IRQ_Pos [1/2]

#define EWIC_EVENTMASK_IRQ_Pos   0U

EWIC EVENTMASKA: IRQ Position

◆ EWIC_EVENTMASK_IRQ_Pos [2/2]

#define EWIC_EVENTMASK_IRQ_Pos   0U

EWIC EVENTMASKA: IRQ Position

◆ EWIC_EVENTMASKA_EDBGREQ_Msk [1/2]

#define EWIC_EVENTMASKA_EDBGREQ_Msk   (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos)

EWIC EVENTMASKA: EDBGREQ Mask

◆ EWIC_EVENTMASKA_EDBGREQ_Msk [2/2]

#define EWIC_EVENTMASKA_EDBGREQ_Msk   (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos)

EWIC EVENTMASKA: EDBGREQ Mask

◆ EWIC_EVENTMASKA_EDBGREQ_Pos [1/2]

#define EWIC_EVENTMASKA_EDBGREQ_Pos   2U

EWIC EVENTMASKA: EDBGREQ Position

◆ EWIC_EVENTMASKA_EDBGREQ_Pos [2/2]

#define EWIC_EVENTMASKA_EDBGREQ_Pos   2U

EWIC EVENTMASKA: EDBGREQ Position

◆ EWIC_EVENTMASKA_EVENT_Msk [1/2]

#define EWIC_EVENTMASKA_EVENT_Msk   (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/)

EWIC EVENTMASKA: EVENT Mask

◆ EWIC_EVENTMASKA_EVENT_Msk [2/2]

#define EWIC_EVENTMASKA_EVENT_Msk   (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/)

EWIC EVENTMASKA: EVENT Mask

◆ EWIC_EVENTMASKA_EVENT_Pos [1/2]

#define EWIC_EVENTMASKA_EVENT_Pos   0U

EWIC EVENTMASKA: EVENT Position

◆ EWIC_EVENTMASKA_EVENT_Pos [2/2]

#define EWIC_EVENTMASKA_EVENT_Pos   0U

EWIC EVENTMASKA: EVENT Position

◆ EWIC_EVENTMASKA_NMI_Msk [1/2]

#define EWIC_EVENTMASKA_NMI_Msk   (0x1UL << EWIC_EVENTMASKA_NMI_Pos)

EWIC EVENTMASKA: NMI Mask

◆ EWIC_EVENTMASKA_NMI_Msk [2/2]

#define EWIC_EVENTMASKA_NMI_Msk   (0x1UL << EWIC_EVENTMASKA_NMI_Pos)

EWIC EVENTMASKA: NMI Mask

◆ EWIC_EVENTMASKA_NMI_Pos [1/2]

#define EWIC_EVENTMASKA_NMI_Pos   1U

EWIC EVENTMASKA: NMI Position

◆ EWIC_EVENTMASKA_NMI_Pos [2/2]

#define EWIC_EVENTMASKA_NMI_Pos   1U

EWIC EVENTMASKA: NMI Position

◆ EWIC_EVENTSPR_EDBGREQ_Msk [1/2]

#define EWIC_EVENTSPR_EDBGREQ_Msk   (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos)

EWIC EVENTSPR: EDBGREQ Mask

◆ EWIC_EVENTSPR_EDBGREQ_Msk [2/2]

#define EWIC_EVENTSPR_EDBGREQ_Msk   (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos)

EWIC EVENTSPR: EDBGREQ Mask

◆ EWIC_EVENTSPR_EDBGREQ_Pos [1/2]

#define EWIC_EVENTSPR_EDBGREQ_Pos   2U

EWIC EVENTSPR: EDBGREQ Position

◆ EWIC_EVENTSPR_EDBGREQ_Pos [2/2]

#define EWIC_EVENTSPR_EDBGREQ_Pos   2U

EWIC EVENTSPR: EDBGREQ Position

◆ EWIC_EVENTSPR_EVENT_Msk [1/2]

#define EWIC_EVENTSPR_EVENT_Msk   (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/)

EWIC EVENTSPR: EVENT Mask

◆ EWIC_EVENTSPR_EVENT_Msk [2/2]

#define EWIC_EVENTSPR_EVENT_Msk   (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/)

EWIC EVENTSPR: EVENT Mask

◆ EWIC_EVENTSPR_EVENT_Pos [1/2]

#define EWIC_EVENTSPR_EVENT_Pos   0U

EWIC EVENTSPR: EVENT Position

◆ EWIC_EVENTSPR_EVENT_Pos [2/2]

#define EWIC_EVENTSPR_EVENT_Pos   0U

EWIC EVENTSPR: EVENT Position

◆ EWIC_EVENTSPR_NMI_Msk [1/2]

#define EWIC_EVENTSPR_NMI_Msk   (0x1UL << EWIC_EVENTSPR_NMI_Pos)

EWIC EVENTSPR: NMI Mask

◆ EWIC_EVENTSPR_NMI_Msk [2/2]

#define EWIC_EVENTSPR_NMI_Msk   (0x1UL << EWIC_EVENTSPR_NMI_Pos)

EWIC EVENTSPR: NMI Mask

◆ EWIC_EVENTSPR_NMI_Pos [1/2]

#define EWIC_EVENTSPR_NMI_Pos   1U

EWIC EVENTSPR: NMI Position

◆ EWIC_EVENTSPR_NMI_Pos [2/2]

#define EWIC_EVENTSPR_NMI_Pos   1U

EWIC EVENTSPR: NMI Position

◆ FPU_FPDSCR_FZ16_Msk [1/3]

#define FPU_FPDSCR_FZ16_Msk   (1UL << FPU_FPDSCR_FZ16_Pos)

FPDSCR: FZ16 bit Mask

◆ FPU_FPDSCR_FZ16_Msk [2/3]

#define FPU_FPDSCR_FZ16_Msk   (1UL << FPU_FPDSCR_FZ16_Pos)

FPDSCR: FZ16 bit Mask

◆ FPU_FPDSCR_FZ16_Msk [3/3]

#define FPU_FPDSCR_FZ16_Msk   (1UL << FPU_FPDSCR_FZ16_Pos)

FPDSCR: FZ16 bit Mask

◆ FPU_FPDSCR_FZ16_Pos [1/3]

#define FPU_FPDSCR_FZ16_Pos   19U

FPDSCR: FZ16 bit Position

◆ FPU_FPDSCR_FZ16_Pos [2/3]

#define FPU_FPDSCR_FZ16_Pos   19U

FPDSCR: FZ16 bit Position

◆ FPU_FPDSCR_FZ16_Pos [3/3]

#define FPU_FPDSCR_FZ16_Pos   19U

FPDSCR: FZ16 bit Position

◆ FPU_FPDSCR_LTPSIZE_Msk [1/3]

#define FPU_FPDSCR_LTPSIZE_Msk   (7UL << FPU_FPDSCR_LTPSIZE_Pos)

FPDSCR: LTPSIZE bit Mask

◆ FPU_FPDSCR_LTPSIZE_Msk [2/3]

#define FPU_FPDSCR_LTPSIZE_Msk   (7UL << FPU_FPDSCR_LTPSIZE_Pos)

FPDSCR: LTPSIZE bit Mask

◆ FPU_FPDSCR_LTPSIZE_Msk [3/3]

#define FPU_FPDSCR_LTPSIZE_Msk   (7UL << FPU_FPDSCR_LTPSIZE_Pos)

FPDSCR: LTPSIZE bit Mask

◆ FPU_FPDSCR_LTPSIZE_Pos [1/3]

#define FPU_FPDSCR_LTPSIZE_Pos   16U

FPDSCR: LTPSIZE bit Position

◆ FPU_FPDSCR_LTPSIZE_Pos [2/3]

#define FPU_FPDSCR_LTPSIZE_Pos   16U

FPDSCR: LTPSIZE bit Position

◆ FPU_FPDSCR_LTPSIZE_Pos [3/3]

#define FPU_FPDSCR_LTPSIZE_Pos   16U

FPDSCR: LTPSIZE bit Position

◆ FPU_MVFR0_FPDivide_Msk [1/3]

#define FPU_MVFR0_FPDivide_Msk   (0xFUL << FPU_MVFR0_FPDivide_Pos)

MVFR0: Divide bits Mask

◆ FPU_MVFR0_FPDivide_Msk [2/3]

#define FPU_MVFR0_FPDivide_Msk   (0xFUL << FPU_MVFR0_FPDivide_Pos)

MVFR0: Divide bits Mask

◆ FPU_MVFR0_FPDivide_Msk [3/3]

#define FPU_MVFR0_FPDivide_Msk   (0xFUL << FPU_MVFR0_FPDivide_Pos)

MVFR0: Divide bits Mask

◆ FPU_MVFR0_FPDivide_Pos [1/3]

#define FPU_MVFR0_FPDivide_Pos   16U

MVFR0: FPDivide bits Position

◆ FPU_MVFR0_FPDivide_Pos [2/3]

#define FPU_MVFR0_FPDivide_Pos   16U

MVFR0: FPDivide bits Position

◆ FPU_MVFR0_FPDivide_Pos [3/3]

#define FPU_MVFR0_FPDivide_Pos   16U

MVFR0: FPDivide bits Position

◆ FPU_MVFR0_FPDP_Msk [1/3]

#define FPU_MVFR0_FPDP_Msk   (0xFUL << FPU_MVFR0_FPDP_Pos)

MVFR0: FPDP bits Mask

◆ FPU_MVFR0_FPDP_Msk [2/3]

#define FPU_MVFR0_FPDP_Msk   (0xFUL << FPU_MVFR0_FPDP_Pos)

MVFR0: FPDP bits Mask

◆ FPU_MVFR0_FPDP_Msk [3/3]

#define FPU_MVFR0_FPDP_Msk   (0xFUL << FPU_MVFR0_FPDP_Pos)

MVFR0: FPDP bits Mask

◆ FPU_MVFR0_FPDP_Pos [1/3]

#define FPU_MVFR0_FPDP_Pos   8U

MVFR0: FPDP bits Position

◆ FPU_MVFR0_FPDP_Pos [2/3]

#define FPU_MVFR0_FPDP_Pos   8U

MVFR0: FPDP bits Position

◆ FPU_MVFR0_FPDP_Pos [3/3]

#define FPU_MVFR0_FPDP_Pos   8U

MVFR0: FPDP bits Position

◆ FPU_MVFR0_FPRound_Msk [1/3]

#define FPU_MVFR0_FPRound_Msk   (0xFUL << FPU_MVFR0_FPRound_Pos)

MVFR0: FPRound bits Mask

◆ FPU_MVFR0_FPRound_Msk [2/3]

#define FPU_MVFR0_FPRound_Msk   (0xFUL << FPU_MVFR0_FPRound_Pos)

MVFR0: FPRound bits Mask

◆ FPU_MVFR0_FPRound_Msk [3/3]

#define FPU_MVFR0_FPRound_Msk   (0xFUL << FPU_MVFR0_FPRound_Pos)

MVFR0: FPRound bits Mask

◆ FPU_MVFR0_FPRound_Pos [1/3]

#define FPU_MVFR0_FPRound_Pos   28U

MVFR0: FPRound bits Position

◆ FPU_MVFR0_FPRound_Pos [2/3]

#define FPU_MVFR0_FPRound_Pos   28U

MVFR0: FPRound bits Position

◆ FPU_MVFR0_FPRound_Pos [3/3]

#define FPU_MVFR0_FPRound_Pos   28U

MVFR0: FPRound bits Position

◆ FPU_MVFR0_FPSP_Msk [1/3]

#define FPU_MVFR0_FPSP_Msk   (0xFUL << FPU_MVFR0_FPSP_Pos)

MVFR0: FPSP bits Mask

◆ FPU_MVFR0_FPSP_Msk [2/3]

#define FPU_MVFR0_FPSP_Msk   (0xFUL << FPU_MVFR0_FPSP_Pos)

MVFR0: FPSP bits Mask

◆ FPU_MVFR0_FPSP_Msk [3/3]

#define FPU_MVFR0_FPSP_Msk   (0xFUL << FPU_MVFR0_FPSP_Pos)

MVFR0: FPSP bits Mask

◆ FPU_MVFR0_FPSP_Pos [1/3]

#define FPU_MVFR0_FPSP_Pos   4U

MVFR0: FPSP bits Position

◆ FPU_MVFR0_FPSP_Pos [2/3]

#define FPU_MVFR0_FPSP_Pos   4U

MVFR0: FPSP bits Position

◆ FPU_MVFR0_FPSP_Pos [3/3]

#define FPU_MVFR0_FPSP_Pos   4U

MVFR0: FPSP bits Position

◆ FPU_MVFR0_FPSqrt_Msk [1/3]

#define FPU_MVFR0_FPSqrt_Msk   (0xFUL << FPU_MVFR0_FPSqrt_Pos)

MVFR0: FPSqrt bits Mask

◆ FPU_MVFR0_FPSqrt_Msk [2/3]

#define FPU_MVFR0_FPSqrt_Msk   (0xFUL << FPU_MVFR0_FPSqrt_Pos)

MVFR0: FPSqrt bits Mask

◆ FPU_MVFR0_FPSqrt_Msk [3/3]

#define FPU_MVFR0_FPSqrt_Msk   (0xFUL << FPU_MVFR0_FPSqrt_Pos)

MVFR0: FPSqrt bits Mask

◆ FPU_MVFR0_FPSqrt_Pos [1/3]

#define FPU_MVFR0_FPSqrt_Pos   20U

MVFR0: FPSqrt bits Position

◆ FPU_MVFR0_FPSqrt_Pos [2/3]

#define FPU_MVFR0_FPSqrt_Pos   20U

MVFR0: FPSqrt bits Position

◆ FPU_MVFR0_FPSqrt_Pos [3/3]

#define FPU_MVFR0_FPSqrt_Pos   20U

MVFR0: FPSqrt bits Position

◆ FPU_MVFR0_SIMDReg_Msk [1/3]

#define FPU_MVFR0_SIMDReg_Msk   (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/)

MVFR0: SIMDReg bits Mask

◆ FPU_MVFR0_SIMDReg_Msk [2/3]

#define FPU_MVFR0_SIMDReg_Msk   (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/)

MVFR0: SIMDReg bits Mask

◆ FPU_MVFR0_SIMDReg_Msk [3/3]

#define FPU_MVFR0_SIMDReg_Msk   (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/)

MVFR0: SIMDReg bits Mask

◆ FPU_MVFR0_SIMDReg_Pos [1/3]

#define FPU_MVFR0_SIMDReg_Pos   0U

MVFR0: SIMDReg bits Position

◆ FPU_MVFR0_SIMDReg_Pos [2/3]

#define FPU_MVFR0_SIMDReg_Pos   0U

MVFR0: SIMDReg bits Position

◆ FPU_MVFR0_SIMDReg_Pos [3/3]

#define FPU_MVFR0_SIMDReg_Pos   0U

MVFR0: SIMDReg bits Position

◆ FPU_MVFR1_FMAC_Msk [1/3]

#define FPU_MVFR1_FMAC_Msk   (0xFUL << FPU_MVFR1_FMAC_Pos)

MVFR1: FMAC bits Mask

◆ FPU_MVFR1_FMAC_Msk [2/3]

#define FPU_MVFR1_FMAC_Msk   (0xFUL << FPU_MVFR1_FMAC_Pos)

MVFR1: FMAC bits Mask

◆ FPU_MVFR1_FMAC_Msk [3/3]

#define FPU_MVFR1_FMAC_Msk   (0xFUL << FPU_MVFR1_FMAC_Pos)

MVFR1: FMAC bits Mask

◆ FPU_MVFR1_FMAC_Pos [1/3]

#define FPU_MVFR1_FMAC_Pos   28U

MVFR1: FMAC bits Position

◆ FPU_MVFR1_FMAC_Pos [2/3]

#define FPU_MVFR1_FMAC_Pos   28U

MVFR1: FMAC bits Position

◆ FPU_MVFR1_FMAC_Pos [3/3]

#define FPU_MVFR1_FMAC_Pos   28U

MVFR1: FMAC bits Position

◆ FPU_MVFR1_FP16_Msk [1/3]

#define FPU_MVFR1_FP16_Msk   (0xFUL << FPU_MVFR1_FP16_Pos)

MVFR1: FP16 bits Mask

◆ FPU_MVFR1_FP16_Msk [2/3]

#define FPU_MVFR1_FP16_Msk   (0xFUL << FPU_MVFR1_FP16_Pos)

MVFR1: FP16 bits Mask

◆ FPU_MVFR1_FP16_Msk [3/3]

#define FPU_MVFR1_FP16_Msk   (0xFUL << FPU_MVFR1_FP16_Pos)

MVFR1: FP16 bits Mask

◆ FPU_MVFR1_FP16_Pos [1/3]

#define FPU_MVFR1_FP16_Pos   20U

MVFR1: FP16 bits Position

◆ FPU_MVFR1_FP16_Pos [2/3]

#define FPU_MVFR1_FP16_Pos   20U

MVFR1: FP16 bits Position

◆ FPU_MVFR1_FP16_Pos [3/3]

#define FPU_MVFR1_FP16_Pos   20U

MVFR1: FP16 bits Position

◆ FPU_MVFR1_FPDNaN_Msk [1/3]

#define FPU_MVFR1_FPDNaN_Msk   (0xFUL << FPU_MVFR1_FPDNaN_Pos)

MVFR1: FPDNaN bits Mask

◆ FPU_MVFR1_FPDNaN_Msk [2/3]

#define FPU_MVFR1_FPDNaN_Msk   (0xFUL << FPU_MVFR1_FPDNaN_Pos)

MVFR1: FPDNaN bits Mask

◆ FPU_MVFR1_FPDNaN_Msk [3/3]

#define FPU_MVFR1_FPDNaN_Msk   (0xFUL << FPU_MVFR1_FPDNaN_Pos)

MVFR1: FPDNaN bits Mask

◆ FPU_MVFR1_FPDNaN_Pos [1/3]

#define FPU_MVFR1_FPDNaN_Pos   4U

MVFR1: FPDNaN bits Position

◆ FPU_MVFR1_FPDNaN_Pos [2/3]

#define FPU_MVFR1_FPDNaN_Pos   4U

MVFR1: FPDNaN bits Position

◆ FPU_MVFR1_FPDNaN_Pos [3/3]

#define FPU_MVFR1_FPDNaN_Pos   4U

MVFR1: FPDNaN bits Position

◆ FPU_MVFR1_FPFtZ_Msk [1/3]

#define FPU_MVFR1_FPFtZ_Msk   (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/)

MVFR1: FPFtZ bits Mask

◆ FPU_MVFR1_FPFtZ_Msk [2/3]

#define FPU_MVFR1_FPFtZ_Msk   (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/)

MVFR1: FPFtZ bits Mask

◆ FPU_MVFR1_FPFtZ_Msk [3/3]

#define FPU_MVFR1_FPFtZ_Msk   (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/)

MVFR1: FPFtZ bits Mask

◆ FPU_MVFR1_FPFtZ_Pos [1/3]

#define FPU_MVFR1_FPFtZ_Pos   0U

MVFR1: FPFtZ bits Position

◆ FPU_MVFR1_FPFtZ_Pos [2/3]

#define FPU_MVFR1_FPFtZ_Pos   0U

MVFR1: FPFtZ bits Position

◆ FPU_MVFR1_FPFtZ_Pos [3/3]

#define FPU_MVFR1_FPFtZ_Pos   0U

MVFR1: FPFtZ bits Position

◆ FPU_MVFR1_FPHP_Msk [1/3]

#define FPU_MVFR1_FPHP_Msk   (0xFUL << FPU_MVFR1_FPHP_Pos)

MVFR1: FPHP bits Mask

◆ FPU_MVFR1_FPHP_Msk [2/3]

#define FPU_MVFR1_FPHP_Msk   (0xFUL << FPU_MVFR1_FPHP_Pos)

MVFR1: FPHP bits Mask

◆ FPU_MVFR1_FPHP_Msk [3/3]

#define FPU_MVFR1_FPHP_Msk   (0xFUL << FPU_MVFR1_FPHP_Pos)

MVFR1: FPHP bits Mask

◆ FPU_MVFR1_FPHP_Pos [1/3]

#define FPU_MVFR1_FPHP_Pos   24U

MVFR1: FPHP bits Position

◆ FPU_MVFR1_FPHP_Pos [2/3]

#define FPU_MVFR1_FPHP_Pos   24U

MVFR1: FPHP bits Position

◆ FPU_MVFR1_FPHP_Pos [3/3]

#define FPU_MVFR1_FPHP_Pos   24U

MVFR1: FPHP bits Position

◆ FPU_MVFR1_MVE_Msk [1/3]

#define FPU_MVFR1_MVE_Msk   (0xFUL << FPU_MVFR1_MVE_Pos)

MVFR1: MVE bits Mask

◆ FPU_MVFR1_MVE_Msk [2/3]

#define FPU_MVFR1_MVE_Msk   (0xFUL << FPU_MVFR1_MVE_Pos)

MVFR1: MVE bits Mask

◆ FPU_MVFR1_MVE_Msk [3/3]

#define FPU_MVFR1_MVE_Msk   (0xFUL << FPU_MVFR1_MVE_Pos)

MVFR1: MVE bits Mask

◆ FPU_MVFR1_MVE_Pos [1/3]

#define FPU_MVFR1_MVE_Pos   8U

MVFR1: MVE bits Position

◆ FPU_MVFR1_MVE_Pos [2/3]

#define FPU_MVFR1_MVE_Pos   8U

MVFR1: MVE bits Position

◆ FPU_MVFR1_MVE_Pos [3/3]

#define FPU_MVFR1_MVE_Pos   8U

MVFR1: MVE bits Position

◆ ICB [1/2]

#define ICB   ((ICB_Type *) SCS_BASE )

System control Register not in SCB

◆ ICB [2/2]

#define ICB   ((ICB_Type *) SCS_BASE )

System control Register not in SCB

◆ ICB_ACTLR_DISCRITAXIRUR_Msk [1/2]

#define ICB_ACTLR_DISCRITAXIRUR_Msk   (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos)

ACTLR: DISCRITAXIRUR Mask

◆ ICB_ACTLR_DISCRITAXIRUR_Msk [2/2]

#define ICB_ACTLR_DISCRITAXIRUR_Msk   (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos)

ACTLR: DISCRITAXIRUR Mask

◆ ICB_ACTLR_DISCRITAXIRUR_Pos [1/2]

#define ICB_ACTLR_DISCRITAXIRUR_Pos   15U

ACTLR: DISCRITAXIRUR Position

◆ ICB_ACTLR_DISCRITAXIRUR_Pos [2/2]

#define ICB_ACTLR_DISCRITAXIRUR_Pos   15U

ACTLR: DISCRITAXIRUR Position

◆ ICB_ACTLR_DISCRITAXIRUW_Msk [1/2]

#define ICB_ACTLR_DISCRITAXIRUW_Msk   (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos)

ACTLR: DISCRITAXIRUW Mask

◆ ICB_ACTLR_DISCRITAXIRUW_Msk [2/2]

#define ICB_ACTLR_DISCRITAXIRUW_Msk   (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos)

ACTLR: DISCRITAXIRUW Mask

◆ ICB_ACTLR_DISCRITAXIRUW_Pos [1/2]

#define ICB_ACTLR_DISCRITAXIRUW_Pos   27U

ACTLR: DISCRITAXIRUW Position

◆ ICB_ACTLR_DISCRITAXIRUW_Pos [2/2]

#define ICB_ACTLR_DISCRITAXIRUW_Pos   27U

ACTLR: DISCRITAXIRUW Position

◆ ICB_ACTLR_DISITMATBFLUSH_Msk [1/2]

#define ICB_ACTLR_DISITMATBFLUSH_Msk   (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos)

ACTLR: DISITMATBFLUSH Mask

◆ ICB_ACTLR_DISITMATBFLUSH_Msk [2/2]

#define ICB_ACTLR_DISITMATBFLUSH_Msk   (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos)

ACTLR: DISITMATBFLUSH Mask

◆ ICB_ACTLR_DISITMATBFLUSH_Pos [1/2]

#define ICB_ACTLR_DISITMATBFLUSH_Pos   12U

ACTLR: DISITMATBFLUSH Position

◆ ICB_ACTLR_DISITMATBFLUSH_Pos [2/2]

#define ICB_ACTLR_DISITMATBFLUSH_Pos   12U

ACTLR: DISITMATBFLUSH Position

◆ ICB_ACTLR_DISNWAMODE_Msk [1/2]

#define ICB_ACTLR_DISNWAMODE_Msk   (1UL << ICB_ACTLR_DISNWAMODE_Pos)

ACTLR: DISNWAMODE Mask

◆ ICB_ACTLR_DISNWAMODE_Msk [2/2]

#define ICB_ACTLR_DISNWAMODE_Msk   (1UL << ICB_ACTLR_DISNWAMODE_Pos)

ACTLR: DISNWAMODE Mask

◆ ICB_ACTLR_DISNWAMODE_Pos [1/2]

#define ICB_ACTLR_DISNWAMODE_Pos   11U

ACTLR: DISNWAMODE Position

◆ ICB_ACTLR_DISNWAMODE_Pos [2/2]

#define ICB_ACTLR_DISNWAMODE_Pos   11U

ACTLR: DISNWAMODE Position

◆ ICB_ACTLR_EVENTBUSEN_Msk [1/2]

#define ICB_ACTLR_EVENTBUSEN_Msk   (1UL << ICB_ACTLR_EVENTBUSEN_Pos)

ACTLR: EVENTBUSEN Mask

◆ ICB_ACTLR_EVENTBUSEN_Msk [2/2]

#define ICB_ACTLR_EVENTBUSEN_Msk   (1UL << ICB_ACTLR_EVENTBUSEN_Pos)

ACTLR: EVENTBUSEN Mask

◆ ICB_ACTLR_EVENTBUSEN_Pos [1/2]

#define ICB_ACTLR_EVENTBUSEN_Pos   14U

ACTLR: EVENTBUSEN Position

◆ ICB_ACTLR_EVENTBUSEN_Pos [2/2]

#define ICB_ACTLR_EVENTBUSEN_Pos   14U

ACTLR: EVENTBUSEN Position

◆ ICB_ACTLR_EVENTBUSEN_S_Msk [1/2]

#define ICB_ACTLR_EVENTBUSEN_S_Msk   (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos)

ACTLR: EVENTBUSEN_S Mask

◆ ICB_ACTLR_EVENTBUSEN_S_Msk [2/2]

#define ICB_ACTLR_EVENTBUSEN_S_Msk   (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos)

ACTLR: EVENTBUSEN_S Mask

◆ ICB_ACTLR_EVENTBUSEN_S_Pos [1/2]

#define ICB_ACTLR_EVENTBUSEN_S_Pos   13U

ACTLR: EVENTBUSEN_S Position

◆ ICB_ACTLR_EVENTBUSEN_S_Pos [2/2]

#define ICB_ACTLR_EVENTBUSEN_S_Pos   13U

ACTLR: EVENTBUSEN_S Position

◆ ICB_ACTLR_FPEXCODIS_Msk [1/2]

#define ICB_ACTLR_FPEXCODIS_Msk   (1UL << ICB_ACTLR_FPEXCODIS_Pos)

ACTLR: FPEXCODIS Mask

◆ ICB_ACTLR_FPEXCODIS_Msk [2/2]

#define ICB_ACTLR_FPEXCODIS_Msk   (1UL << ICB_ACTLR_FPEXCODIS_Pos)

ACTLR: FPEXCODIS Mask

◆ ICB_ACTLR_FPEXCODIS_Pos [1/2]

#define ICB_ACTLR_FPEXCODIS_Pos   10U

ACTLR: FPEXCODIS Position

◆ ICB_ACTLR_FPEXCODIS_Pos [2/2]

#define ICB_ACTLR_FPEXCODIS_Pos   10U

ACTLR: FPEXCODIS Position

◆ ICB_ICTR_INTLINESNUM_Msk [1/2]

#define ICB_ICTR_INTLINESNUM_Msk   (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/)

ICTR: INTLINESNUM Mask

◆ ICB_ICTR_INTLINESNUM_Msk [2/2]

#define ICB_ICTR_INTLINESNUM_Msk   (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/)

ICTR: INTLINESNUM Mask

◆ ICB_ICTR_INTLINESNUM_Pos [1/2]

#define ICB_ICTR_INTLINESNUM_Pos   0U

ICTR: INTLINESNUM Position

◆ ICB_ICTR_INTLINESNUM_Pos [2/2]

#define ICB_ICTR_INTLINESNUM_Pos   0U

ICTR: INTLINESNUM Position

◆ MEMSYSCTL [1/2]

#define MEMSYSCTL   ((MemSysCtl_Type *) MEMSYSCTL_BASE )

Memory System Control configuration struct

◆ MEMSYSCTL [2/2]

#define MEMSYSCTL   ((MemSysCtl_Type *) MEMSYSCTL_BASE )

Memory System Control configuration struct

◆ MEMSYSCTL_BASE [1/2]

#define MEMSYSCTL_BASE   (0xE001E000UL)

Memory System Control Base Address

◆ MEMSYSCTL_BASE [2/2]

#define MEMSYSCTL_BASE   (0xE001E000UL)

Memory System Control Base Address

◆ MEMSYSCTL_DTCMCR_EN_Msk [1/2]

#define MEMSYSCTL_DTCMCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/)

MEMSYSCTL DTCMCR: EN Mask

◆ MEMSYSCTL_DTCMCR_EN_Msk [2/2]

#define MEMSYSCTL_DTCMCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/)

MEMSYSCTL DTCMCR: EN Mask

◆ MEMSYSCTL_DTCMCR_EN_Pos [1/2]

#define MEMSYSCTL_DTCMCR_EN_Pos   0U

MEMSYSCTL DTCMCR: EN Position

◆ MEMSYSCTL_DTCMCR_EN_Pos [2/2]

#define MEMSYSCTL_DTCMCR_EN_Pos   0U

MEMSYSCTL DTCMCR: EN Position

◆ MEMSYSCTL_DTCMCR_SZ_Msk [1/2]

#define MEMSYSCTL_DTCMCR_SZ_Msk   (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos)

MEMSYSCTL DTCMCR: SZ Mask

◆ MEMSYSCTL_DTCMCR_SZ_Msk [2/2]

#define MEMSYSCTL_DTCMCR_SZ_Msk   (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos)

MEMSYSCTL DTCMCR: SZ Mask

◆ MEMSYSCTL_DTCMCR_SZ_Pos [1/2]

#define MEMSYSCTL_DTCMCR_SZ_Pos   3U

MEMSYSCTL DTCMCR: SZ Position

◆ MEMSYSCTL_DTCMCR_SZ_Pos [2/2]

#define MEMSYSCTL_DTCMCR_SZ_Pos   3U

MEMSYSCTL DTCMCR: SZ Position

◆ MEMSYSCTL_DTGU_CFG_BLKSZ_Msk [1/2]

#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk   (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/)

MEMSYSCTL DTGU_CFG: BLKSZ Mask

◆ MEMSYSCTL_DTGU_CFG_BLKSZ_Msk [2/2]

#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk   (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/)

MEMSYSCTL DTGU_CFG: BLKSZ Mask

◆ MEMSYSCTL_DTGU_CFG_BLKSZ_Pos [1/2]

#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos   0U

MEMSYSCTL DTGU_CFG: BLKSZ Position

◆ MEMSYSCTL_DTGU_CFG_BLKSZ_Pos [2/2]

#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos   0U

MEMSYSCTL DTGU_CFG: BLKSZ Position

◆ MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk [1/2]

#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk   (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos)

MEMSYSCTL DTGU_CFG: NUMBLKS Mask

◆ MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk [2/2]

#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk   (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos)

MEMSYSCTL DTGU_CFG: NUMBLKS Mask

◆ MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos [1/2]

#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos   8U

MEMSYSCTL DTGU_CFG: NUMBLKS Position

◆ MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos [2/2]

#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos   8U

MEMSYSCTL DTGU_CFG: NUMBLKS Position

◆ MEMSYSCTL_DTGU_CFG_PRESENT_Msk [1/2]

#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk   (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos)

MEMSYSCTL DTGU_CFG: PRESENT Mask

◆ MEMSYSCTL_DTGU_CFG_PRESENT_Msk [2/2]

#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk   (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos)

MEMSYSCTL DTGU_CFG: PRESENT Mask

◆ MEMSYSCTL_DTGU_CFG_PRESENT_Pos [1/2]

#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos   31U

MEMSYSCTL DTGU_CFG: PRESENT Position

◆ MEMSYSCTL_DTGU_CFG_PRESENT_Pos [2/2]

#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos   31U

MEMSYSCTL DTGU_CFG: PRESENT Position

◆ MEMSYSCTL_DTGU_CTRL_DBFEN_Msk [1/2]

#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk   (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/)

MEMSYSCTL DTGU_CTRL: DBFEN Mask

◆ MEMSYSCTL_DTGU_CTRL_DBFEN_Msk [2/2]

#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk   (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/)

MEMSYSCTL DTGU_CTRL: DBFEN Mask

◆ MEMSYSCTL_DTGU_CTRL_DBFEN_Pos [1/2]

#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos   0U

MEMSYSCTL DTGU_CTRL: DBFEN Position

◆ MEMSYSCTL_DTGU_CTRL_DBFEN_Pos [2/2]

#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos   0U

MEMSYSCTL DTGU_CTRL: DBFEN Position

◆ MEMSYSCTL_DTGU_CTRL_DEREN_Msk [1/2]

#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk   (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos)

MEMSYSCTL DTGU_CTRL: DEREN Mask

◆ MEMSYSCTL_DTGU_CTRL_DEREN_Msk [2/2]

#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk   (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos)

MEMSYSCTL DTGU_CTRL: DEREN Mask

◆ MEMSYSCTL_DTGU_CTRL_DEREN_Pos [1/2]

#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos   1U

MEMSYSCTL DTGU_CTRL: DEREN Position

◆ MEMSYSCTL_DTGU_CTRL_DEREN_Pos [2/2]

#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos   1U

MEMSYSCTL DTGU_CTRL: DEREN Position

◆ MEMSYSCTL_ITCMCR_EN_Msk [1/2]

#define MEMSYSCTL_ITCMCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/)

MEMSYSCTL ITCMCR: EN Mask

◆ MEMSYSCTL_ITCMCR_EN_Msk [2/2]

#define MEMSYSCTL_ITCMCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/)

MEMSYSCTL ITCMCR: EN Mask

◆ MEMSYSCTL_ITCMCR_EN_Pos [1/2]

#define MEMSYSCTL_ITCMCR_EN_Pos   0U

MEMSYSCTL ITCMCR: EN Position

◆ MEMSYSCTL_ITCMCR_EN_Pos [2/2]

#define MEMSYSCTL_ITCMCR_EN_Pos   0U

MEMSYSCTL ITCMCR: EN Position

◆ MEMSYSCTL_ITCMCR_SZ_Msk [1/2]

#define MEMSYSCTL_ITCMCR_SZ_Msk   (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos)

MEMSYSCTL ITCMCR: SZ Mask

◆ MEMSYSCTL_ITCMCR_SZ_Msk [2/2]

#define MEMSYSCTL_ITCMCR_SZ_Msk   (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos)

MEMSYSCTL ITCMCR: SZ Mask

◆ MEMSYSCTL_ITCMCR_SZ_Pos [1/2]

#define MEMSYSCTL_ITCMCR_SZ_Pos   3U

MEMSYSCTL ITCMCR: SZ Position

◆ MEMSYSCTL_ITCMCR_SZ_Pos [2/2]

#define MEMSYSCTL_ITCMCR_SZ_Pos   3U

MEMSYSCTL ITCMCR: SZ Position

◆ MEMSYSCTL_ITGU_CFG_BLKSZ_Msk [1/2]

#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk   (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/)

MEMSYSCTL ITGU_CFG: BLKSZ Mask

◆ MEMSYSCTL_ITGU_CFG_BLKSZ_Msk [2/2]

#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk   (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/)

MEMSYSCTL ITGU_CFG: BLKSZ Mask

◆ MEMSYSCTL_ITGU_CFG_BLKSZ_Pos [1/2]

#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos   0U

MEMSYSCTL ITGU_CFG: BLKSZ Position

◆ MEMSYSCTL_ITGU_CFG_BLKSZ_Pos [2/2]

#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos   0U

MEMSYSCTL ITGU_CFG: BLKSZ Position

◆ MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk [1/2]

#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk   (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos)

MEMSYSCTL ITGU_CFG: NUMBLKS Mask

◆ MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk [2/2]

#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk   (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos)

MEMSYSCTL ITGU_CFG: NUMBLKS Mask

◆ MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos [1/2]

#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos   8U

MEMSYSCTL ITGU_CFG: NUMBLKS Position

◆ MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos [2/2]

#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos   8U

MEMSYSCTL ITGU_CFG: NUMBLKS Position

◆ MEMSYSCTL_ITGU_CFG_PRESENT_Msk [1/2]

#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk   (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos)

MEMSYSCTL ITGU_CFG: PRESENT Mask

◆ MEMSYSCTL_ITGU_CFG_PRESENT_Msk [2/2]

#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk   (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos)

MEMSYSCTL ITGU_CFG: PRESENT Mask

◆ MEMSYSCTL_ITGU_CFG_PRESENT_Pos [1/2]

#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos   31U

MEMSYSCTL ITGU_CFG: PRESENT Position

◆ MEMSYSCTL_ITGU_CFG_PRESENT_Pos [2/2]

#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos   31U

MEMSYSCTL ITGU_CFG: PRESENT Position

◆ MEMSYSCTL_ITGU_CTRL_DBFEN_Msk [1/2]

#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk   (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/)

MEMSYSCTL ITGU_CTRL: DBFEN Mask

◆ MEMSYSCTL_ITGU_CTRL_DBFEN_Msk [2/2]

#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk   (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/)

MEMSYSCTL ITGU_CTRL: DBFEN Mask

◆ MEMSYSCTL_ITGU_CTRL_DBFEN_Pos [1/2]

#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos   0U

MEMSYSCTL ITGU_CTRL: DBFEN Position

◆ MEMSYSCTL_ITGU_CTRL_DBFEN_Pos [2/2]

#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos   0U

MEMSYSCTL ITGU_CTRL: DBFEN Position

◆ MEMSYSCTL_ITGU_CTRL_DEREN_Msk [1/2]

#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk   (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos)

MEMSYSCTL ITGU_CTRL: DEREN Mask

◆ MEMSYSCTL_ITGU_CTRL_DEREN_Msk [2/2]

#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk   (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos)

MEMSYSCTL ITGU_CTRL: DEREN Mask

◆ MEMSYSCTL_ITGU_CTRL_DEREN_Pos [1/2]

#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos   1U

MEMSYSCTL ITGU_CTRL: DEREN Position

◆ MEMSYSCTL_ITGU_CTRL_DEREN_Pos [2/2]

#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos   1U

MEMSYSCTL ITGU_CTRL: DEREN Position

◆ MEMSYSCTL_MSCR_CPWRDN_Msk [1/2]

#define MEMSYSCTL_MSCR_CPWRDN_Msk   (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos)

MEMSYSCTL MSCR: CPWRDN Mask

◆ MEMSYSCTL_MSCR_CPWRDN_Msk [2/2]

#define MEMSYSCTL_MSCR_CPWRDN_Msk   (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos)

MEMSYSCTL MSCR: CPWRDN Mask

◆ MEMSYSCTL_MSCR_CPWRDN_Pos [1/2]

#define MEMSYSCTL_MSCR_CPWRDN_Pos   17U

MEMSYSCTL MSCR: CPWRDN Position

◆ MEMSYSCTL_MSCR_CPWRDN_Pos [2/2]

#define MEMSYSCTL_MSCR_CPWRDN_Pos   17U

MEMSYSCTL MSCR: CPWRDN Position

◆ MEMSYSCTL_MSCR_DCACTIVE_Msk [1/2]

#define MEMSYSCTL_MSCR_DCACTIVE_Msk   (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos)

MEMSYSCTL MSCR: DCACTIVE Mask

◆ MEMSYSCTL_MSCR_DCACTIVE_Msk [2/2]

#define MEMSYSCTL_MSCR_DCACTIVE_Msk   (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos)

MEMSYSCTL MSCR: DCACTIVE Mask

◆ MEMSYSCTL_MSCR_DCACTIVE_Pos [1/2]

#define MEMSYSCTL_MSCR_DCACTIVE_Pos   12U

MEMSYSCTL MSCR: DCACTIVE Position

◆ MEMSYSCTL_MSCR_DCACTIVE_Pos [2/2]

#define MEMSYSCTL_MSCR_DCACTIVE_Pos   12U

MEMSYSCTL MSCR: DCACTIVE Position

◆ MEMSYSCTL_MSCR_DCCLEAN_Msk [1/2]

#define MEMSYSCTL_MSCR_DCCLEAN_Msk   (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos)

MEMSYSCTL MSCR: DCCLEAN Mask

◆ MEMSYSCTL_MSCR_DCCLEAN_Msk [2/2]

#define MEMSYSCTL_MSCR_DCCLEAN_Msk   (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos)

MEMSYSCTL MSCR: DCCLEAN Mask

◆ MEMSYSCTL_MSCR_DCCLEAN_Pos [1/2]

#define MEMSYSCTL_MSCR_DCCLEAN_Pos   16U

MEMSYSCTL MSCR: DCCLEAN Position

◆ MEMSYSCTL_MSCR_DCCLEAN_Pos [2/2]

#define MEMSYSCTL_MSCR_DCCLEAN_Pos   16U

MEMSYSCTL MSCR: DCCLEAN Position

◆ MEMSYSCTL_MSCR_ECCEN_Msk [1/2]

#define MEMSYSCTL_MSCR_ECCEN_Msk   (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos)

MEMSYSCTL MSCR: ECCEN Mask

◆ MEMSYSCTL_MSCR_ECCEN_Msk [2/2]

#define MEMSYSCTL_MSCR_ECCEN_Msk   (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos)

MEMSYSCTL MSCR: ECCEN Mask

◆ MEMSYSCTL_MSCR_ECCEN_Pos [1/2]

#define MEMSYSCTL_MSCR_ECCEN_Pos   1U

MEMSYSCTL MSCR: ECCEN Position

◆ MEMSYSCTL_MSCR_ECCEN_Pos [2/2]

#define MEMSYSCTL_MSCR_ECCEN_Pos   1U

MEMSYSCTL MSCR: ECCEN Position

◆ MEMSYSCTL_MSCR_EVECCFAULT_Msk [1/2]

#define MEMSYSCTL_MSCR_EVECCFAULT_Msk   (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos)

MEMSYSCTL MSCR: EVECCFAULT Mask

◆ MEMSYSCTL_MSCR_EVECCFAULT_Msk [2/2]

#define MEMSYSCTL_MSCR_EVECCFAULT_Msk   (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos)

MEMSYSCTL MSCR: EVECCFAULT Mask

◆ MEMSYSCTL_MSCR_EVECCFAULT_Pos [1/2]

#define MEMSYSCTL_MSCR_EVECCFAULT_Pos   3U

MEMSYSCTL MSCR: EVECCFAULT Position

◆ MEMSYSCTL_MSCR_EVECCFAULT_Pos [2/2]

#define MEMSYSCTL_MSCR_EVECCFAULT_Pos   3U

MEMSYSCTL MSCR: EVECCFAULT Position

◆ MEMSYSCTL_MSCR_FORCEWT_Msk [1/2]

#define MEMSYSCTL_MSCR_FORCEWT_Msk   (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos)

MEMSYSCTL MSCR: FORCEWT Mask

◆ MEMSYSCTL_MSCR_FORCEWT_Msk [2/2]

#define MEMSYSCTL_MSCR_FORCEWT_Msk   (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos)

MEMSYSCTL MSCR: FORCEWT Mask

◆ MEMSYSCTL_MSCR_FORCEWT_Pos [1/2]

#define MEMSYSCTL_MSCR_FORCEWT_Pos   2U

MEMSYSCTL MSCR: FORCEWT Position

◆ MEMSYSCTL_MSCR_FORCEWT_Pos [2/2]

#define MEMSYSCTL_MSCR_FORCEWT_Pos   2U

MEMSYSCTL MSCR: FORCEWT Position

◆ MEMSYSCTL_MSCR_ICACTIVE_Msk [1/2]

#define MEMSYSCTL_MSCR_ICACTIVE_Msk   (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos)

MEMSYSCTL MSCR: ICACTIVE Mask

◆ MEMSYSCTL_MSCR_ICACTIVE_Msk [2/2]

#define MEMSYSCTL_MSCR_ICACTIVE_Msk   (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos)

MEMSYSCTL MSCR: ICACTIVE Mask

◆ MEMSYSCTL_MSCR_ICACTIVE_Pos [1/2]

#define MEMSYSCTL_MSCR_ICACTIVE_Pos   13U

MEMSYSCTL MSCR: ICACTIVE Position

◆ MEMSYSCTL_MSCR_ICACTIVE_Pos [2/2]

#define MEMSYSCTL_MSCR_ICACTIVE_Pos   13U

MEMSYSCTL MSCR: ICACTIVE Position

◆ MEMSYSCTL_PAHBCR_EN_Msk [1/2]

#define MEMSYSCTL_PAHBCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/)

MEMSYSCTL PAHBCR: EN Mask

◆ MEMSYSCTL_PAHBCR_EN_Msk [2/2]

#define MEMSYSCTL_PAHBCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/)

MEMSYSCTL PAHBCR: EN Mask

◆ MEMSYSCTL_PAHBCR_EN_Pos [1/2]

#define MEMSYSCTL_PAHBCR_EN_Pos   0U

MEMSYSCTL PAHBCR: EN Position

◆ MEMSYSCTL_PAHBCR_EN_Pos [2/2]

#define MEMSYSCTL_PAHBCR_EN_Pos   0U

MEMSYSCTL PAHBCR: EN Position

◆ MEMSYSCTL_PAHBCR_SZ_Msk [1/2]

#define MEMSYSCTL_PAHBCR_SZ_Msk   (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos)

MEMSYSCTL PAHBCR: SZ Mask

◆ MEMSYSCTL_PAHBCR_SZ_Msk [2/2]

#define MEMSYSCTL_PAHBCR_SZ_Msk   (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos)

MEMSYSCTL PAHBCR: SZ Mask

◆ MEMSYSCTL_PAHBCR_SZ_Pos [1/2]

#define MEMSYSCTL_PAHBCR_SZ_Pos   1U

MEMSYSCTL PAHBCR: SZ Position

◆ MEMSYSCTL_PAHBCR_SZ_Pos [2/2]

#define MEMSYSCTL_PAHBCR_SZ_Pos   1U

MEMSYSCTL PAHBCR: SZ Position

◆ MEMSYSCTL_PFCR_DIS_NLP_Msk

#define MEMSYSCTL_PFCR_DIS_NLP_Msk   (0x1UL << MEMSYSCTL_PFCR_DIS_NLP_Pos)

MEMSYSCTL PFCR: DIS_NLP Mask

◆ MEMSYSCTL_PFCR_DIS_NLP_Pos

#define MEMSYSCTL_PFCR_DIS_NLP_Pos   7U

MEMSYSCTL PFCR: DIS_NLP Position

◆ MEMSYSCTL_PFCR_ENABLE_Msk [1/2]

#define MEMSYSCTL_PFCR_ENABLE_Msk   (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/)

MEMSYSCTL PFCR: ENABLE Mask

◆ MEMSYSCTL_PFCR_ENABLE_Msk [2/2]

#define MEMSYSCTL_PFCR_ENABLE_Msk   (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/)

MEMSYSCTL PFCR: ENABLE Mask

◆ MEMSYSCTL_PFCR_ENABLE_Pos [1/2]

#define MEMSYSCTL_PFCR_ENABLE_Pos   0U

MEMSYSCTL PFCR: ENABLE Position

◆ MEMSYSCTL_PFCR_ENABLE_Pos [2/2]

#define MEMSYSCTL_PFCR_ENABLE_Pos   0U

MEMSYSCTL PFCR: ENABLE Position

◆ MPU_RASR_AP_Msk [1/6]

#define MPU_RASR_AP_Msk   (0x7UL << MPU_RASR_AP_Pos)

MPU RASR: ATTRS.AP Mask

◆ MPU_RASR_AP_Msk [2/6]

#define MPU_RASR_AP_Msk   (0x7UL << MPU_RASR_AP_Pos)

MPU RASR: ATTRS.AP Mask

◆ MPU_RASR_AP_Msk [3/6]

#define MPU_RASR_AP_Msk   (0x7UL << MPU_RASR_AP_Pos)

MPU RASR: ATTRS.AP Mask

◆ MPU_RASR_AP_Msk [4/6]

#define MPU_RASR_AP_Msk   (0x7UL << MPU_RASR_AP_Pos)

MPU RASR: ATTRS.AP Mask

◆ MPU_RASR_AP_Msk [5/6]

#define MPU_RASR_AP_Msk   (0x7UL << MPU_RASR_AP_Pos)

MPU RASR: ATTRS.AP Mask

◆ MPU_RASR_AP_Msk [6/6]

#define MPU_RASR_AP_Msk   (0x7UL << MPU_RASR_AP_Pos)

MPU RASR: ATTRS.AP Mask

◆ MPU_RASR_AP_Pos [1/6]

#define MPU_RASR_AP_Pos   24U

MPU RASR: ATTRS.AP Position

◆ MPU_RASR_AP_Pos [2/6]

#define MPU_RASR_AP_Pos   24U

MPU RASR: ATTRS.AP Position

◆ MPU_RASR_AP_Pos [3/6]

#define MPU_RASR_AP_Pos   24U

MPU RASR: ATTRS.AP Position

◆ MPU_RASR_AP_Pos [4/6]

#define MPU_RASR_AP_Pos   24U

MPU RASR: ATTRS.AP Position

◆ MPU_RASR_AP_Pos [5/6]

#define MPU_RASR_AP_Pos   24U

MPU RASR: ATTRS.AP Position

◆ MPU_RASR_AP_Pos [6/6]

#define MPU_RASR_AP_Pos   24U

MPU RASR: ATTRS.AP Position

◆ MPU_RASR_ATTRS_Msk [1/6]

#define MPU_RASR_ATTRS_Msk   (0xFFFFUL << MPU_RASR_ATTRS_Pos)

MPU RASR: MPU Region Attribute field Mask

◆ MPU_RASR_ATTRS_Msk [2/6]

#define MPU_RASR_ATTRS_Msk   (0xFFFFUL << MPU_RASR_ATTRS_Pos)

MPU RASR: MPU Region Attribute field Mask

◆ MPU_RASR_ATTRS_Msk [3/6]

#define MPU_RASR_ATTRS_Msk   (0xFFFFUL << MPU_RASR_ATTRS_Pos)

MPU RASR: MPU Region Attribute field Mask

◆ MPU_RASR_ATTRS_Msk [4/6]

#define MPU_RASR_ATTRS_Msk   (0xFFFFUL << MPU_RASR_ATTRS_Pos)

MPU RASR: MPU Region Attribute field Mask

◆ MPU_RASR_ATTRS_Msk [5/6]

#define MPU_RASR_ATTRS_Msk   (0xFFFFUL << MPU_RASR_ATTRS_Pos)

MPU RASR: MPU Region Attribute field Mask

◆ MPU_RASR_ATTRS_Msk [6/6]

#define MPU_RASR_ATTRS_Msk   (0xFFFFUL << MPU_RASR_ATTRS_Pos)

MPU RASR: MPU Region Attribute field Mask

◆ MPU_RASR_ATTRS_Pos [1/6]

#define MPU_RASR_ATTRS_Pos   16U

MPU RASR: MPU Region Attribute field Position

◆ MPU_RASR_ATTRS_Pos [2/6]

#define MPU_RASR_ATTRS_Pos   16U

MPU RASR: MPU Region Attribute field Position

◆ MPU_RASR_ATTRS_Pos [3/6]

#define MPU_RASR_ATTRS_Pos   16U

MPU RASR: MPU Region Attribute field Position

◆ MPU_RASR_ATTRS_Pos [4/6]

#define MPU_RASR_ATTRS_Pos   16U

MPU RASR: MPU Region Attribute field Position

◆ MPU_RASR_ATTRS_Pos [5/6]

#define MPU_RASR_ATTRS_Pos   16U

MPU RASR: MPU Region Attribute field Position

◆ MPU_RASR_ATTRS_Pos [6/6]

#define MPU_RASR_ATTRS_Pos   16U

MPU RASR: MPU Region Attribute field Position

◆ MPU_RASR_B_Msk [1/6]

#define MPU_RASR_B_Msk   (1UL << MPU_RASR_B_Pos)

MPU RASR: ATTRS.B Mask

◆ MPU_RASR_B_Msk [2/6]

#define MPU_RASR_B_Msk   (1UL << MPU_RASR_B_Pos)

MPU RASR: ATTRS.B Mask

◆ MPU_RASR_B_Msk [3/6]

#define MPU_RASR_B_Msk   (1UL << MPU_RASR_B_Pos)

MPU RASR: ATTRS.B Mask

◆ MPU_RASR_B_Msk [4/6]

#define MPU_RASR_B_Msk   (1UL << MPU_RASR_B_Pos)

MPU RASR: ATTRS.B Mask

◆ MPU_RASR_B_Msk [5/6]

#define MPU_RASR_B_Msk   (1UL << MPU_RASR_B_Pos)

MPU RASR: ATTRS.B Mask

◆ MPU_RASR_B_Msk [6/6]

#define MPU_RASR_B_Msk   (1UL << MPU_RASR_B_Pos)

MPU RASR: ATTRS.B Mask

◆ MPU_RASR_B_Pos [1/6]

#define MPU_RASR_B_Pos   16U

MPU RASR: ATTRS.B Position

◆ MPU_RASR_B_Pos [2/6]

#define MPU_RASR_B_Pos   16U

MPU RASR: ATTRS.B Position

◆ MPU_RASR_B_Pos [3/6]

#define MPU_RASR_B_Pos   16U

MPU RASR: ATTRS.B Position

◆ MPU_RASR_B_Pos [4/6]

#define MPU_RASR_B_Pos   16U

MPU RASR: ATTRS.B Position

◆ MPU_RASR_B_Pos [5/6]

#define MPU_RASR_B_Pos   16U

MPU RASR: ATTRS.B Position

◆ MPU_RASR_B_Pos [6/6]

#define MPU_RASR_B_Pos   16U

MPU RASR: ATTRS.B Position

◆ MPU_RASR_C_Msk [1/6]

#define MPU_RASR_C_Msk   (1UL << MPU_RASR_C_Pos)

MPU RASR: ATTRS.C Mask

◆ MPU_RASR_C_Msk [2/6]

#define MPU_RASR_C_Msk   (1UL << MPU_RASR_C_Pos)

MPU RASR: ATTRS.C Mask

◆ MPU_RASR_C_Msk [3/6]

#define MPU_RASR_C_Msk   (1UL << MPU_RASR_C_Pos)

MPU RASR: ATTRS.C Mask

◆ MPU_RASR_C_Msk [4/6]

#define MPU_RASR_C_Msk   (1UL << MPU_RASR_C_Pos)

MPU RASR: ATTRS.C Mask

◆ MPU_RASR_C_Msk [5/6]

#define MPU_RASR_C_Msk   (1UL << MPU_RASR_C_Pos)

MPU RASR: ATTRS.C Mask

◆ MPU_RASR_C_Msk [6/6]

#define MPU_RASR_C_Msk   (1UL << MPU_RASR_C_Pos)

MPU RASR: ATTRS.C Mask

◆ MPU_RASR_C_Pos [1/6]

#define MPU_RASR_C_Pos   17U

MPU RASR: ATTRS.C Position

◆ MPU_RASR_C_Pos [2/6]

#define MPU_RASR_C_Pos   17U

MPU RASR: ATTRS.C Position

◆ MPU_RASR_C_Pos [3/6]

#define MPU_RASR_C_Pos   17U

MPU RASR: ATTRS.C Position

◆ MPU_RASR_C_Pos [4/6]

#define MPU_RASR_C_Pos   17U

MPU RASR: ATTRS.C Position

◆ MPU_RASR_C_Pos [5/6]

#define MPU_RASR_C_Pos   17U

MPU RASR: ATTRS.C Position

◆ MPU_RASR_C_Pos [6/6]

#define MPU_RASR_C_Pos   17U

MPU RASR: ATTRS.C Position

◆ MPU_RASR_ENABLE_Msk [1/6]

#define MPU_RASR_ENABLE_Msk   (1UL /*<< MPU_RASR_ENABLE_Pos*/)

MPU RASR: Region enable bit Disable Mask

◆ MPU_RASR_ENABLE_Msk [2/6]

#define MPU_RASR_ENABLE_Msk   (1UL /*<< MPU_RASR_ENABLE_Pos*/)

MPU RASR: Region enable bit Disable Mask

◆ MPU_RASR_ENABLE_Msk [3/6]

#define MPU_RASR_ENABLE_Msk   (1UL /*<< MPU_RASR_ENABLE_Pos*/)

MPU RASR: Region enable bit Disable Mask

◆ MPU_RASR_ENABLE_Msk [4/6]

#define MPU_RASR_ENABLE_Msk   (1UL /*<< MPU_RASR_ENABLE_Pos*/)

MPU RASR: Region enable bit Disable Mask

◆ MPU_RASR_ENABLE_Msk [5/6]

#define MPU_RASR_ENABLE_Msk   (1UL /*<< MPU_RASR_ENABLE_Pos*/)

MPU RASR: Region enable bit Disable Mask

◆ MPU_RASR_ENABLE_Msk [6/6]

#define MPU_RASR_ENABLE_Msk   (1UL /*<< MPU_RASR_ENABLE_Pos*/)

MPU RASR: Region enable bit Disable Mask

◆ MPU_RASR_ENABLE_Pos [1/6]

#define MPU_RASR_ENABLE_Pos   0U

MPU RASR: Region enable bit Position

◆ MPU_RASR_ENABLE_Pos [2/6]

#define MPU_RASR_ENABLE_Pos   0U

MPU RASR: Region enable bit Position

◆ MPU_RASR_ENABLE_Pos [3/6]

#define MPU_RASR_ENABLE_Pos   0U

MPU RASR: Region enable bit Position

◆ MPU_RASR_ENABLE_Pos [4/6]

#define MPU_RASR_ENABLE_Pos   0U

MPU RASR: Region enable bit Position

◆ MPU_RASR_ENABLE_Pos [5/6]

#define MPU_RASR_ENABLE_Pos   0U

MPU RASR: Region enable bit Position

◆ MPU_RASR_ENABLE_Pos [6/6]

#define MPU_RASR_ENABLE_Pos   0U

MPU RASR: Region enable bit Position

◆ MPU_RASR_S_Msk [1/6]

#define MPU_RASR_S_Msk   (1UL << MPU_RASR_S_Pos)

MPU RASR: ATTRS.S Mask

◆ MPU_RASR_S_Msk [2/6]

#define MPU_RASR_S_Msk   (1UL << MPU_RASR_S_Pos)

MPU RASR: ATTRS.S Mask

◆ MPU_RASR_S_Msk [3/6]

#define MPU_RASR_S_Msk   (1UL << MPU_RASR_S_Pos)

MPU RASR: ATTRS.S Mask

◆ MPU_RASR_S_Msk [4/6]

#define MPU_RASR_S_Msk   (1UL << MPU_RASR_S_Pos)

MPU RASR: ATTRS.S Mask

◆ MPU_RASR_S_Msk [5/6]

#define MPU_RASR_S_Msk   (1UL << MPU_RASR_S_Pos)

MPU RASR: ATTRS.S Mask

◆ MPU_RASR_S_Msk [6/6]

#define MPU_RASR_S_Msk   (1UL << MPU_RASR_S_Pos)

MPU RASR: ATTRS.S Mask

◆ MPU_RASR_S_Pos [1/6]

#define MPU_RASR_S_Pos   18U

MPU RASR: ATTRS.S Position

◆ MPU_RASR_S_Pos [2/6]

#define MPU_RASR_S_Pos   18U

MPU RASR: ATTRS.S Position

◆ MPU_RASR_S_Pos [3/6]

#define MPU_RASR_S_Pos   18U

MPU RASR: ATTRS.S Position

◆ MPU_RASR_S_Pos [4/6]

#define MPU_RASR_S_Pos   18U

MPU RASR: ATTRS.S Position

◆ MPU_RASR_S_Pos [5/6]

#define MPU_RASR_S_Pos   18U

MPU RASR: ATTRS.S Position

◆ MPU_RASR_S_Pos [6/6]

#define MPU_RASR_S_Pos   18U

MPU RASR: ATTRS.S Position

◆ MPU_RASR_SIZE_Msk [1/6]

#define MPU_RASR_SIZE_Msk   (0x1FUL << MPU_RASR_SIZE_Pos)

MPU RASR: Region Size Field Mask

◆ MPU_RASR_SIZE_Msk [2/6]

#define MPU_RASR_SIZE_Msk   (0x1FUL << MPU_RASR_SIZE_Pos)

MPU RASR: Region Size Field Mask

◆ MPU_RASR_SIZE_Msk [3/6]

#define MPU_RASR_SIZE_Msk   (0x1FUL << MPU_RASR_SIZE_Pos)

MPU RASR: Region Size Field Mask

◆ MPU_RASR_SIZE_Msk [4/6]

#define MPU_RASR_SIZE_Msk   (0x1FUL << MPU_RASR_SIZE_Pos)

MPU RASR: Region Size Field Mask

◆ MPU_RASR_SIZE_Msk [5/6]

#define MPU_RASR_SIZE_Msk   (0x1FUL << MPU_RASR_SIZE_Pos)

MPU RASR: Region Size Field Mask

◆ MPU_RASR_SIZE_Msk [6/6]

#define MPU_RASR_SIZE_Msk   (0x1FUL << MPU_RASR_SIZE_Pos)

MPU RASR: Region Size Field Mask

◆ MPU_RASR_SIZE_Pos [1/6]

#define MPU_RASR_SIZE_Pos   1U

MPU RASR: Region Size Field Position

◆ MPU_RASR_SIZE_Pos [2/6]

#define MPU_RASR_SIZE_Pos   1U

MPU RASR: Region Size Field Position

◆ MPU_RASR_SIZE_Pos [3/6]

#define MPU_RASR_SIZE_Pos   1U

MPU RASR: Region Size Field Position

◆ MPU_RASR_SIZE_Pos [4/6]

#define MPU_RASR_SIZE_Pos   1U

MPU RASR: Region Size Field Position

◆ MPU_RASR_SIZE_Pos [5/6]

#define MPU_RASR_SIZE_Pos   1U

MPU RASR: Region Size Field Position

◆ MPU_RASR_SIZE_Pos [6/6]

#define MPU_RASR_SIZE_Pos   1U

MPU RASR: Region Size Field Position

◆ MPU_RASR_SRD_Msk [1/6]

#define MPU_RASR_SRD_Msk   (0xFFUL << MPU_RASR_SRD_Pos)

MPU RASR: Sub-Region Disable Mask

◆ MPU_RASR_SRD_Msk [2/6]

#define MPU_RASR_SRD_Msk   (0xFFUL << MPU_RASR_SRD_Pos)

MPU RASR: Sub-Region Disable Mask

◆ MPU_RASR_SRD_Msk [3/6]

#define MPU_RASR_SRD_Msk   (0xFFUL << MPU_RASR_SRD_Pos)

MPU RASR: Sub-Region Disable Mask

◆ MPU_RASR_SRD_Msk [4/6]

#define MPU_RASR_SRD_Msk   (0xFFUL << MPU_RASR_SRD_Pos)

MPU RASR: Sub-Region Disable Mask

◆ MPU_RASR_SRD_Msk [5/6]

#define MPU_RASR_SRD_Msk   (0xFFUL << MPU_RASR_SRD_Pos)

MPU RASR: Sub-Region Disable Mask

◆ MPU_RASR_SRD_Msk [6/6]

#define MPU_RASR_SRD_Msk   (0xFFUL << MPU_RASR_SRD_Pos)

MPU RASR: Sub-Region Disable Mask

◆ MPU_RASR_SRD_Pos [1/6]

#define MPU_RASR_SRD_Pos   8U

MPU RASR: Sub-Region Disable Position

◆ MPU_RASR_SRD_Pos [2/6]

#define MPU_RASR_SRD_Pos   8U

MPU RASR: Sub-Region Disable Position

◆ MPU_RASR_SRD_Pos [3/6]

#define MPU_RASR_SRD_Pos   8U

MPU RASR: Sub-Region Disable Position

◆ MPU_RASR_SRD_Pos [4/6]

#define MPU_RASR_SRD_Pos   8U

MPU RASR: Sub-Region Disable Position

◆ MPU_RASR_SRD_Pos [5/6]

#define MPU_RASR_SRD_Pos   8U

MPU RASR: Sub-Region Disable Position

◆ MPU_RASR_SRD_Pos [6/6]

#define MPU_RASR_SRD_Pos   8U

MPU RASR: Sub-Region Disable Position

◆ MPU_RASR_TEX_Msk [1/6]

#define MPU_RASR_TEX_Msk   (0x7UL << MPU_RASR_TEX_Pos)

MPU RASR: ATTRS.TEX Mask

◆ MPU_RASR_TEX_Msk [2/6]

#define MPU_RASR_TEX_Msk   (0x7UL << MPU_RASR_TEX_Pos)

MPU RASR: ATTRS.TEX Mask

◆ MPU_RASR_TEX_Msk [3/6]

#define MPU_RASR_TEX_Msk   (0x7UL << MPU_RASR_TEX_Pos)

MPU RASR: ATTRS.TEX Mask

◆ MPU_RASR_TEX_Msk [4/6]

#define MPU_RASR_TEX_Msk   (0x7UL << MPU_RASR_TEX_Pos)

MPU RASR: ATTRS.TEX Mask

◆ MPU_RASR_TEX_Msk [5/6]

#define MPU_RASR_TEX_Msk   (0x7UL << MPU_RASR_TEX_Pos)

MPU RASR: ATTRS.TEX Mask

◆ MPU_RASR_TEX_Msk [6/6]

#define MPU_RASR_TEX_Msk   (0x7UL << MPU_RASR_TEX_Pos)

MPU RASR: ATTRS.TEX Mask

◆ MPU_RASR_TEX_Pos [1/6]

#define MPU_RASR_TEX_Pos   19U

MPU RASR: ATTRS.TEX Position

◆ MPU_RASR_TEX_Pos [2/6]

#define MPU_RASR_TEX_Pos   19U

MPU RASR: ATTRS.TEX Position

◆ MPU_RASR_TEX_Pos [3/6]

#define MPU_RASR_TEX_Pos   19U

MPU RASR: ATTRS.TEX Position

◆ MPU_RASR_TEX_Pos [4/6]

#define MPU_RASR_TEX_Pos   19U

MPU RASR: ATTRS.TEX Position

◆ MPU_RASR_TEX_Pos [5/6]

#define MPU_RASR_TEX_Pos   19U

MPU RASR: ATTRS.TEX Position

◆ MPU_RASR_TEX_Pos [6/6]

#define MPU_RASR_TEX_Pos   19U

MPU RASR: ATTRS.TEX Position

◆ MPU_RASR_XN_Msk [1/6]

#define MPU_RASR_XN_Msk   (1UL << MPU_RASR_XN_Pos)

MPU RASR: ATTRS.XN Mask

◆ MPU_RASR_XN_Msk [2/6]

#define MPU_RASR_XN_Msk   (1UL << MPU_RASR_XN_Pos)

MPU RASR: ATTRS.XN Mask

◆ MPU_RASR_XN_Msk [3/6]

#define MPU_RASR_XN_Msk   (1UL << MPU_RASR_XN_Pos)

MPU RASR: ATTRS.XN Mask

◆ MPU_RASR_XN_Msk [4/6]

#define MPU_RASR_XN_Msk   (1UL << MPU_RASR_XN_Pos)

MPU RASR: ATTRS.XN Mask

◆ MPU_RASR_XN_Msk [5/6]

#define MPU_RASR_XN_Msk   (1UL << MPU_RASR_XN_Pos)

MPU RASR: ATTRS.XN Mask

◆ MPU_RASR_XN_Msk [6/6]

#define MPU_RASR_XN_Msk   (1UL << MPU_RASR_XN_Pos)

MPU RASR: ATTRS.XN Mask

◆ MPU_RASR_XN_Pos [1/6]

#define MPU_RASR_XN_Pos   28U

MPU RASR: ATTRS.XN Position

◆ MPU_RASR_XN_Pos [2/6]

#define MPU_RASR_XN_Pos   28U

MPU RASR: ATTRS.XN Position

◆ MPU_RASR_XN_Pos [3/6]

#define MPU_RASR_XN_Pos   28U

MPU RASR: ATTRS.XN Position

◆ MPU_RASR_XN_Pos [4/6]

#define MPU_RASR_XN_Pos   28U

MPU RASR: ATTRS.XN Position

◆ MPU_RASR_XN_Pos [5/6]

#define MPU_RASR_XN_Pos   28U

MPU RASR: ATTRS.XN Position

◆ MPU_RASR_XN_Pos [6/6]

#define MPU_RASR_XN_Pos   28U

MPU RASR: ATTRS.XN Position

◆ MPU_RBAR_ADDR_Msk [1/6]

#define MPU_RBAR_ADDR_Msk   (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)

MPU RBAR: ADDR Mask

◆ MPU_RBAR_ADDR_Msk [2/6]

#define MPU_RBAR_ADDR_Msk   (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)

MPU RBAR: ADDR Mask

◆ MPU_RBAR_ADDR_Msk [3/6]

#define MPU_RBAR_ADDR_Msk   (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)

MPU RBAR: ADDR Mask

◆ MPU_RBAR_ADDR_Msk [4/6]

#define MPU_RBAR_ADDR_Msk   (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)

MPU RBAR: ADDR Mask

◆ MPU_RBAR_ADDR_Msk [5/6]

#define MPU_RBAR_ADDR_Msk   (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)

MPU RBAR: ADDR Mask

◆ MPU_RBAR_ADDR_Msk [6/6]

#define MPU_RBAR_ADDR_Msk   (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)

MPU RBAR: ADDR Mask

◆ MPU_RBAR_ADDR_Pos [1/6]

#define MPU_RBAR_ADDR_Pos   8U

MPU RBAR: ADDR Position

◆ MPU_RBAR_ADDR_Pos [2/6]

#define MPU_RBAR_ADDR_Pos   5U

MPU RBAR: ADDR Position

◆ MPU_RBAR_ADDR_Pos [3/6]

#define MPU_RBAR_ADDR_Pos   5U

MPU RBAR: ADDR Position

◆ MPU_RBAR_ADDR_Pos [4/6]

#define MPU_RBAR_ADDR_Pos   5U

MPU RBAR: ADDR Position

◆ MPU_RBAR_ADDR_Pos [5/6]

#define MPU_RBAR_ADDR_Pos   8U

MPU RBAR: ADDR Position

◆ MPU_RBAR_ADDR_Pos [6/6]

#define MPU_RBAR_ADDR_Pos   5U

MPU RBAR: ADDR Position

◆ MPU_RBAR_REGION_Msk [1/6]

#define MPU_RBAR_REGION_Msk   (0xFUL /*<< MPU_RBAR_REGION_Pos*/)

MPU RBAR: REGION Mask

◆ MPU_RBAR_REGION_Msk [2/6]

#define MPU_RBAR_REGION_Msk   (0xFUL /*<< MPU_RBAR_REGION_Pos*/)

MPU RBAR: REGION Mask

◆ MPU_RBAR_REGION_Msk [3/6]

#define MPU_RBAR_REGION_Msk   (0xFUL /*<< MPU_RBAR_REGION_Pos*/)

MPU RBAR: REGION Mask

◆ MPU_RBAR_REGION_Msk [4/6]

#define MPU_RBAR_REGION_Msk   (0xFUL /*<< MPU_RBAR_REGION_Pos*/)

MPU RBAR: REGION Mask

◆ MPU_RBAR_REGION_Msk [5/6]

#define MPU_RBAR_REGION_Msk   (0xFUL /*<< MPU_RBAR_REGION_Pos*/)

MPU RBAR: REGION Mask

◆ MPU_RBAR_REGION_Msk [6/6]

#define MPU_RBAR_REGION_Msk   (0xFUL /*<< MPU_RBAR_REGION_Pos*/)

MPU RBAR: REGION Mask

◆ MPU_RBAR_REGION_Pos [1/6]

#define MPU_RBAR_REGION_Pos   0U

MPU RBAR: REGION Position

◆ MPU_RBAR_REGION_Pos [2/6]

#define MPU_RBAR_REGION_Pos   0U

MPU RBAR: REGION Position

◆ MPU_RBAR_REGION_Pos [3/6]

#define MPU_RBAR_REGION_Pos   0U

MPU RBAR: REGION Position

◆ MPU_RBAR_REGION_Pos [4/6]

#define MPU_RBAR_REGION_Pos   0U

MPU RBAR: REGION Position

◆ MPU_RBAR_REGION_Pos [5/6]

#define MPU_RBAR_REGION_Pos   0U

MPU RBAR: REGION Position

◆ MPU_RBAR_REGION_Pos [6/6]

#define MPU_RBAR_REGION_Pos   0U

MPU RBAR: REGION Position

◆ MPU_RBAR_VALID_Msk [1/6]

#define MPU_RBAR_VALID_Msk   (1UL << MPU_RBAR_VALID_Pos)

MPU RBAR: VALID Mask

◆ MPU_RBAR_VALID_Msk [2/6]

#define MPU_RBAR_VALID_Msk   (1UL << MPU_RBAR_VALID_Pos)

MPU RBAR: VALID Mask

◆ MPU_RBAR_VALID_Msk [3/6]

#define MPU_RBAR_VALID_Msk   (1UL << MPU_RBAR_VALID_Pos)

MPU RBAR: VALID Mask

◆ MPU_RBAR_VALID_Msk [4/6]

#define MPU_RBAR_VALID_Msk   (1UL << MPU_RBAR_VALID_Pos)

MPU RBAR: VALID Mask

◆ MPU_RBAR_VALID_Msk [5/6]

#define MPU_RBAR_VALID_Msk   (1UL << MPU_RBAR_VALID_Pos)

MPU RBAR: VALID Mask

◆ MPU_RBAR_VALID_Msk [6/6]

#define MPU_RBAR_VALID_Msk   (1UL << MPU_RBAR_VALID_Pos)

MPU RBAR: VALID Mask

◆ MPU_RBAR_VALID_Pos [1/6]

#define MPU_RBAR_VALID_Pos   4U

MPU RBAR: VALID Position

◆ MPU_RBAR_VALID_Pos [2/6]

#define MPU_RBAR_VALID_Pos   4U

MPU RBAR: VALID Position

◆ MPU_RBAR_VALID_Pos [3/6]

#define MPU_RBAR_VALID_Pos   4U

MPU RBAR: VALID Position

◆ MPU_RBAR_VALID_Pos [4/6]

#define MPU_RBAR_VALID_Pos   4U

MPU RBAR: VALID Position

◆ MPU_RBAR_VALID_Pos [5/6]

#define MPU_RBAR_VALID_Pos   4U

MPU RBAR: VALID Position

◆ MPU_RBAR_VALID_Pos [6/6]

#define MPU_RBAR_VALID_Pos   4U

MPU RBAR: VALID Position

◆ MPU_RLAR_PXN_Msk [1/3]

#define MPU_RLAR_PXN_Msk   (1UL << MPU_RLAR_PXN_Pos)

MPU RLAR: PXN Mask

◆ MPU_RLAR_PXN_Msk [2/3]

#define MPU_RLAR_PXN_Msk   (1UL << MPU_RLAR_PXN_Pos)

MPU RLAR: PXN Mask

◆ MPU_RLAR_PXN_Msk [3/3]

#define MPU_RLAR_PXN_Msk   (1UL << MPU_RLAR_PXN_Pos)

MPU RLAR: PXN Mask

◆ MPU_RLAR_PXN_Pos [1/3]

#define MPU_RLAR_PXN_Pos   4U

MPU RLAR: PXN Position

◆ MPU_RLAR_PXN_Pos [2/3]

#define MPU_RLAR_PXN_Pos   4U

MPU RLAR: PXN Position

◆ MPU_RLAR_PXN_Pos [3/3]

#define MPU_RLAR_PXN_Pos   4U

MPU RLAR: PXN Position

◆ PRCCFGINF [1/2]

#define PRCCFGINF   ((PrcCfgInf_Type *) PRCCFGINF_BASE )

Processor Configuration Information configuration struct

◆ PRCCFGINF [2/2]

#define PRCCFGINF   ((PrcCfgInf_Type *) PRCCFGINF_BASE )

Processor Configuration Information configuration struct

◆ PRCCFGINF_BASE [1/2]

#define PRCCFGINF_BASE   (0xE001E700UL)

Processor Configuration Information Base Address

◆ PRCCFGINF_BASE [2/2]

#define PRCCFGINF_BASE   (0xE001E700UL)

Processor Configuration Information Base Address

◆ PWRMODCTL [1/2]

#define PWRMODCTL   ((PwrModCtl_Type *) PWRMODCTL_BASE )

Power Mode Control configuration struct

◆ PWRMODCTL [2/2]

#define PWRMODCTL   ((PwrModCtl_Type *) PWRMODCTL_BASE )

Power Mode Control configuration struct

◆ PWRMODCTL_BASE [1/2]

#define PWRMODCTL_BASE   (0xE001E300UL)

Power Mode Control Base Address

◆ PWRMODCTL_BASE [2/2]

#define PWRMODCTL_BASE   (0xE001E300UL)

Power Mode Control Base Address

◆ PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk [1/2]

#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk   (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/)

PWRMODCTL CPDLPSTATE: CLPSTATE Mask

◆ PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk [2/2]

#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk   (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/)

PWRMODCTL CPDLPSTATE: CLPSTATE Mask

◆ PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos [1/2]

#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos   0U

PWRMODCTL CPDLPSTATE: CLPSTATE Position

◆ PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos [2/2]

#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos   0U

PWRMODCTL CPDLPSTATE: CLPSTATE Position

◆ PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk [1/2]

#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk   (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos)

PWRMODCTL CPDLPSTATE: ELPSTATE Mask

◆ PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk [2/2]

#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk   (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos)

PWRMODCTL CPDLPSTATE: ELPSTATE Mask

◆ PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos [1/2]

#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos   4U

PWRMODCTL CPDLPSTATE: ELPSTATE Position

◆ PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos [2/2]

#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos   4U

PWRMODCTL CPDLPSTATE: ELPSTATE Position

◆ PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk [1/2]

#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk   (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos)

PWRMODCTL CPDLPSTATE: RLPSTATE Mask

◆ PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk [2/2]

#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk   (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos)

PWRMODCTL CPDLPSTATE: RLPSTATE Mask

◆ PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos [1/2]

#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos   8U

PWRMODCTL CPDLPSTATE: RLPSTATE Position

◆ PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos [2/2]

#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos   8U

PWRMODCTL CPDLPSTATE: RLPSTATE Position

◆ PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk [1/2]

#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk   (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/)

PWRMODCTL DPDLPSTATE: DLPSTATE Mask

◆ PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk [2/2]

#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk   (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/)

PWRMODCTL DPDLPSTATE: DLPSTATE Mask

◆ PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos [1/2]

#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos   0U

PWRMODCTL DPDLPSTATE: DLPSTATE Position

◆ PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos [2/2]

#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos   0U

PWRMODCTL DPDLPSTATE: DLPSTATE Position

◆ SCB_ABFSR_AHBP_Msk

#define SCB_ABFSR_AHBP_Msk   (1UL << SCB_ABFSR_AHBP_Pos)

SCB ABFSR: AHBP Mask

◆ SCB_ABFSR_AHBP_Pos

#define SCB_ABFSR_AHBP_Pos   2U

SCB ABFSR: AHBP Position

◆ SCB_ABFSR_AXIM_Msk

#define SCB_ABFSR_AXIM_Msk   (1UL << SCB_ABFSR_AXIM_Pos)

SCB ABFSR: AXIM Mask

◆ SCB_ABFSR_AXIM_Pos

#define SCB_ABFSR_AXIM_Pos   3U

SCB ABFSR: AXIM Position

◆ SCB_ABFSR_AXIMTYPE_Msk

#define SCB_ABFSR_AXIMTYPE_Msk   (3UL << SCB_ABFSR_AXIMTYPE_Pos)

SCB ABFSR: AXIMTYPE Mask

◆ SCB_ABFSR_AXIMTYPE_Pos

#define SCB_ABFSR_AXIMTYPE_Pos   8U

SCB ABFSR: AXIMTYPE Position

◆ SCB_ABFSR_DTCM_Msk

#define SCB_ABFSR_DTCM_Msk   (1UL << SCB_ABFSR_DTCM_Pos)

SCB ABFSR: DTCM Mask

◆ SCB_ABFSR_DTCM_Pos

#define SCB_ABFSR_DTCM_Pos   1U

SCB ABFSR: DTCM Position

◆ SCB_ABFSR_EPPB_Msk

#define SCB_ABFSR_EPPB_Msk   (1UL << SCB_ABFSR_EPPB_Pos)

SCB ABFSR: EPPB Mask

◆ SCB_ABFSR_EPPB_Pos

#define SCB_ABFSR_EPPB_Pos   4U

SCB ABFSR: EPPB Position

◆ SCB_ABFSR_ITCM_Msk

#define SCB_ABFSR_ITCM_Msk   (1UL /*<< SCB_ABFSR_ITCM_Pos*/)

SCB ABFSR: ITCM Mask

◆ SCB_ABFSR_ITCM_Pos

#define SCB_ABFSR_ITCM_Pos   0U

SCB ABFSR: ITCM Position

◆ SCB_AHBPCR_EN_Msk

#define SCB_AHBPCR_EN_Msk   (1UL /*<< SCB_AHBPCR_EN_Pos*/)

SCB AHBPCR: EN Mask

◆ SCB_AHBPCR_EN_Pos

#define SCB_AHBPCR_EN_Pos   0U

SCB AHBPCR: EN Position

◆ SCB_AHBPCR_SZ_Msk

#define SCB_AHBPCR_SZ_Msk   (7UL << SCB_AHBPCR_SZ_Pos)

SCB AHBPCR: SZ Mask

◆ SCB_AHBPCR_SZ_Pos

#define SCB_AHBPCR_SZ_Pos   1U

SCB AHBPCR: SZ Position

◆ SCB_AHBSCR_CTL_Msk

#define SCB_AHBSCR_CTL_Msk   (3UL /*<< SCB_AHBSCR_CTL_Pos*/)

SCB AHBSCR: CTL Mask

◆ SCB_AHBSCR_CTL_Pos

#define SCB_AHBSCR_CTL_Pos   0U

SCB AHBSCR: CTL Position

◆ SCB_AHBSCR_INITCOUNT_Msk

#define SCB_AHBSCR_INITCOUNT_Msk   (0x1FUL << SCB_AHBSCR_INITCOUNT_Pos)

SCB AHBSCR: INITCOUNT Mask

◆ SCB_AHBSCR_INITCOUNT_Pos

#define SCB_AHBSCR_INITCOUNT_Pos   11U

SCB AHBSCR: INITCOUNT Position

◆ SCB_AHBSCR_TPRI_Msk

#define SCB_AHBSCR_TPRI_Msk   (0x1FFUL << SCB_AHBSCR_TPRI_Pos)

SCB AHBSCR: TPRI Mask

◆ SCB_AHBSCR_TPRI_Pos

#define SCB_AHBSCR_TPRI_Pos   2U

SCB AHBSCR: TPRI Position

◆ SCB_AIRCR_BFHFNMINS_Msk [1/9]

#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

◆ SCB_AIRCR_BFHFNMINS_Msk [2/9]

#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

◆ SCB_AIRCR_BFHFNMINS_Msk [3/9]

#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

◆ SCB_AIRCR_BFHFNMINS_Msk [4/9]

#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

◆ SCB_AIRCR_BFHFNMINS_Msk [5/9]

#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

◆ SCB_AIRCR_BFHFNMINS_Msk [6/9]

#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

◆ SCB_AIRCR_BFHFNMINS_Msk [7/9]

#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

◆ SCB_AIRCR_BFHFNMINS_Msk [8/9]

#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

◆ SCB_AIRCR_BFHFNMINS_Msk [9/9]

#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

◆ SCB_AIRCR_BFHFNMINS_Pos [1/9]

#define SCB_AIRCR_BFHFNMINS_Pos   13U

SCB AIRCR: BFHFNMINS Position

◆ SCB_AIRCR_BFHFNMINS_Pos [2/9]

#define SCB_AIRCR_BFHFNMINS_Pos   13U

SCB AIRCR: BFHFNMINS Position

◆ SCB_AIRCR_BFHFNMINS_Pos [3/9]

#define SCB_AIRCR_BFHFNMINS_Pos   13U

SCB AIRCR: BFHFNMINS Position

◆ SCB_AIRCR_BFHFNMINS_Pos [4/9]

#define SCB_AIRCR_BFHFNMINS_Pos   13U

SCB AIRCR: BFHFNMINS Position

◆ SCB_AIRCR_BFHFNMINS_Pos [5/9]

#define SCB_AIRCR_BFHFNMINS_Pos   13U

SCB AIRCR: BFHFNMINS Position

◆ SCB_AIRCR_BFHFNMINS_Pos [6/9]

#define SCB_AIRCR_BFHFNMINS_Pos   13U

SCB AIRCR: BFHFNMINS Position

◆ SCB_AIRCR_BFHFNMINS_Pos [7/9]

#define SCB_AIRCR_BFHFNMINS_Pos   13U

SCB AIRCR: BFHFNMINS Position

◆ SCB_AIRCR_BFHFNMINS_Pos [8/9]

#define SCB_AIRCR_BFHFNMINS_Pos   13U

SCB AIRCR: BFHFNMINS Position

◆ SCB_AIRCR_BFHFNMINS_Pos [9/9]

#define SCB_AIRCR_BFHFNMINS_Pos   13U

SCB AIRCR: BFHFNMINS Position

◆ SCB_AIRCR_DIT_Msk [1/3]

#define SCB_AIRCR_DIT_Msk   (1UL << SCB_AIRCR_DIT_Pos)

SCB AIRCR: Data Independent Timing Mask

◆ SCB_AIRCR_DIT_Msk [2/3]

#define SCB_AIRCR_DIT_Msk   (1UL << SCB_AIRCR_DIT_Pos)

SCB AIRCR: Data Independent Timing Mask

◆ SCB_AIRCR_DIT_Msk [3/3]

#define SCB_AIRCR_DIT_Msk   (1UL << SCB_AIRCR_DIT_Pos)

SCB AIRCR: Data Independent Timing Mask

◆ SCB_AIRCR_DIT_Pos [1/3]

#define SCB_AIRCR_DIT_Pos   4U

SCB AIRCR: Data Independent Timing Position

◆ SCB_AIRCR_DIT_Pos [2/3]

#define SCB_AIRCR_DIT_Pos   4U

SCB AIRCR: Data Independent Timing Position

◆ SCB_AIRCR_DIT_Pos [3/3]

#define SCB_AIRCR_DIT_Pos   4U

SCB AIRCR: Data Independent Timing Position

◆ SCB_AIRCR_ENDIANESS_Msk [1/17]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

◆ SCB_AIRCR_ENDIANESS_Msk [2/17]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

◆ SCB_AIRCR_ENDIANESS_Msk [3/17]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

◆ SCB_AIRCR_ENDIANESS_Msk [4/17]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

◆ SCB_AIRCR_ENDIANESS_Msk [5/17]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

◆ SCB_AIRCR_ENDIANESS_Msk [6/17]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

◆ SCB_AIRCR_ENDIANESS_Msk [7/17]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

◆ SCB_AIRCR_ENDIANESS_Msk [8/17]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

◆ SCB_AIRCR_ENDIANESS_Msk [9/17]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

◆ SCB_AIRCR_ENDIANESS_Msk [10/17]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

◆ SCB_AIRCR_ENDIANESS_Msk [11/17]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

◆ SCB_AIRCR_ENDIANESS_Msk [12/17]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

◆ SCB_AIRCR_ENDIANESS_Msk [13/17]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

◆ SCB_AIRCR_ENDIANESS_Msk [14/17]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

◆ SCB_AIRCR_ENDIANESS_Msk [15/17]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

◆ SCB_AIRCR_ENDIANESS_Msk [16/17]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

◆ SCB_AIRCR_ENDIANESS_Msk [17/17]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

◆ SCB_AIRCR_ENDIANESS_Pos [1/17]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

◆ SCB_AIRCR_ENDIANESS_Pos [2/17]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

◆ SCB_AIRCR_ENDIANESS_Pos [3/17]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

◆ SCB_AIRCR_ENDIANESS_Pos [4/17]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

◆ SCB_AIRCR_ENDIANESS_Pos [5/17]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

◆ SCB_AIRCR_ENDIANESS_Pos [6/17]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

◆ SCB_AIRCR_ENDIANESS_Pos [7/17]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

◆ SCB_AIRCR_ENDIANESS_Pos [8/17]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

◆ SCB_AIRCR_ENDIANESS_Pos [9/17]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

◆ SCB_AIRCR_ENDIANESS_Pos [10/17]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

◆ SCB_AIRCR_ENDIANESS_Pos [11/17]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

◆ SCB_AIRCR_ENDIANESS_Pos [12/17]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

◆ SCB_AIRCR_ENDIANESS_Pos [13/17]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

◆ SCB_AIRCR_ENDIANESS_Pos [14/17]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

◆ SCB_AIRCR_ENDIANESS_Pos [15/17]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

◆ SCB_AIRCR_ENDIANESS_Pos [16/17]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

◆ SCB_AIRCR_ENDIANESS_Pos [17/17]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

◆ SCB_AIRCR_IESB_Msk [1/3]

#define SCB_AIRCR_IESB_Msk   (1UL << SCB_AIRCR_IESB_Pos)

SCB AIRCR: Implicit ESB Enable Mask

◆ SCB_AIRCR_IESB_Msk [2/3]

#define SCB_AIRCR_IESB_Msk   (1UL << SCB_AIRCR_IESB_Pos)

SCB AIRCR: Implicit ESB Enable Mask

◆ SCB_AIRCR_IESB_Msk [3/3]

#define SCB_AIRCR_IESB_Msk   (1UL << SCB_AIRCR_IESB_Pos)

SCB AIRCR: Implicit ESB Enable Mask

◆ SCB_AIRCR_IESB_Pos [1/3]

#define SCB_AIRCR_IESB_Pos   5U

SCB AIRCR: Implicit ESB Enable Position

◆ SCB_AIRCR_IESB_Pos [2/3]

#define SCB_AIRCR_IESB_Pos   5U

SCB AIRCR: Implicit ESB Enable Position

◆ SCB_AIRCR_IESB_Pos [3/3]

#define SCB_AIRCR_IESB_Pos   5U

SCB AIRCR: Implicit ESB Enable Position

◆ SCB_AIRCR_PRIGROUP_Msk [1/11]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

◆ SCB_AIRCR_PRIGROUP_Msk [2/11]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

◆ SCB_AIRCR_PRIGROUP_Msk [3/11]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

◆ SCB_AIRCR_PRIGROUP_Msk [4/11]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

◆ SCB_AIRCR_PRIGROUP_Msk [5/11]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

◆ SCB_AIRCR_PRIGROUP_Msk [6/11]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

◆ SCB_AIRCR_PRIGROUP_Msk [7/11]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

◆ SCB_AIRCR_PRIGROUP_Msk [8/11]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

◆ SCB_AIRCR_PRIGROUP_Msk [9/11]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

◆ SCB_AIRCR_PRIGROUP_Msk [10/11]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

◆ SCB_AIRCR_PRIGROUP_Msk [11/11]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

◆ SCB_AIRCR_PRIGROUP_Pos [1/11]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

◆ SCB_AIRCR_PRIGROUP_Pos [2/11]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

◆ SCB_AIRCR_PRIGROUP_Pos [3/11]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

◆ SCB_AIRCR_PRIGROUP_Pos [4/11]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

◆ SCB_AIRCR_PRIGROUP_Pos [5/11]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

◆ SCB_AIRCR_PRIGROUP_Pos [6/11]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

◆ SCB_AIRCR_PRIGROUP_Pos [7/11]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

◆ SCB_AIRCR_PRIGROUP_Pos [8/11]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

◆ SCB_AIRCR_PRIGROUP_Pos [9/11]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

◆ SCB_AIRCR_PRIGROUP_Pos [10/11]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

◆ SCB_AIRCR_PRIGROUP_Pos [11/11]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

◆ SCB_AIRCR_PRIS_Msk [1/9]

#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

◆ SCB_AIRCR_PRIS_Msk [2/9]

#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

◆ SCB_AIRCR_PRIS_Msk [3/9]

#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

◆ SCB_AIRCR_PRIS_Msk [4/9]

#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

◆ SCB_AIRCR_PRIS_Msk [5/9]

#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

◆ SCB_AIRCR_PRIS_Msk [6/9]

#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

◆ SCB_AIRCR_PRIS_Msk [7/9]

#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

◆ SCB_AIRCR_PRIS_Msk [8/9]

#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

◆ SCB_AIRCR_PRIS_Msk [9/9]

#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

◆ SCB_AIRCR_PRIS_Pos [1/9]

#define SCB_AIRCR_PRIS_Pos   14U

SCB AIRCR: PRIS Position

◆ SCB_AIRCR_PRIS_Pos [2/9]

#define SCB_AIRCR_PRIS_Pos   14U

SCB AIRCR: PRIS Position

◆ SCB_AIRCR_PRIS_Pos [3/9]

#define SCB_AIRCR_PRIS_Pos   14U

SCB AIRCR: PRIS Position

◆ SCB_AIRCR_PRIS_Pos [4/9]

#define SCB_AIRCR_PRIS_Pos   14U

SCB AIRCR: PRIS Position

◆ SCB_AIRCR_PRIS_Pos [5/9]

#define SCB_AIRCR_PRIS_Pos   14U

SCB AIRCR: PRIS Position

◆ SCB_AIRCR_PRIS_Pos [6/9]

#define SCB_AIRCR_PRIS_Pos   14U

SCB AIRCR: PRIS Position

◆ SCB_AIRCR_PRIS_Pos [7/9]

#define SCB_AIRCR_PRIS_Pos   14U

SCB AIRCR: PRIS Position

◆ SCB_AIRCR_PRIS_Pos [8/9]

#define SCB_AIRCR_PRIS_Pos   14U

SCB AIRCR: PRIS Position

◆ SCB_AIRCR_PRIS_Pos [9/9]

#define SCB_AIRCR_PRIS_Pos   14U

SCB AIRCR: PRIS Position

◆ SCB_AIRCR_SYSRESETREQ_Msk [1/17]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

◆ SCB_AIRCR_SYSRESETREQ_Msk [2/17]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

◆ SCB_AIRCR_SYSRESETREQ_Msk [3/17]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

◆ SCB_AIRCR_SYSRESETREQ_Msk [4/17]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

◆ SCB_AIRCR_SYSRESETREQ_Msk [5/17]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

◆ SCB_AIRCR_SYSRESETREQ_Msk [6/17]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

◆ SCB_AIRCR_SYSRESETREQ_Msk [7/17]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

◆ SCB_AIRCR_SYSRESETREQ_Msk [8/17]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

◆ SCB_AIRCR_SYSRESETREQ_Msk [9/17]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

◆ SCB_AIRCR_SYSRESETREQ_Msk [10/17]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

◆ SCB_AIRCR_SYSRESETREQ_Msk [11/17]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

◆ SCB_AIRCR_SYSRESETREQ_Msk [12/17]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

◆ SCB_AIRCR_SYSRESETREQ_Msk [13/17]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

◆ SCB_AIRCR_SYSRESETREQ_Msk [14/17]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

◆ SCB_AIRCR_SYSRESETREQ_Msk [15/17]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

◆ SCB_AIRCR_SYSRESETREQ_Msk [16/17]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

◆ SCB_AIRCR_SYSRESETREQ_Msk [17/17]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

◆ SCB_AIRCR_SYSRESETREQ_Pos [1/17]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

◆ SCB_AIRCR_SYSRESETREQ_Pos [2/17]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

◆ SCB_AIRCR_SYSRESETREQ_Pos [3/17]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

◆ SCB_AIRCR_SYSRESETREQ_Pos [4/17]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

◆ SCB_AIRCR_SYSRESETREQ_Pos [5/17]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

◆ SCB_AIRCR_SYSRESETREQ_Pos [6/17]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

◆ SCB_AIRCR_SYSRESETREQ_Pos [7/17]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

◆ SCB_AIRCR_SYSRESETREQ_Pos [8/17]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

◆ SCB_AIRCR_SYSRESETREQ_Pos [9/17]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

◆ SCB_AIRCR_SYSRESETREQ_Pos [10/17]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

◆ SCB_AIRCR_SYSRESETREQ_Pos [11/17]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

◆ SCB_AIRCR_SYSRESETREQ_Pos [12/17]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

◆ SCB_AIRCR_SYSRESETREQ_Pos [13/17]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

◆ SCB_AIRCR_SYSRESETREQ_Pos [14/17]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

◆ SCB_AIRCR_SYSRESETREQ_Pos [15/17]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

◆ SCB_AIRCR_SYSRESETREQ_Pos [16/17]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

◆ SCB_AIRCR_SYSRESETREQ_Pos [17/17]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

◆ SCB_AIRCR_SYSRESETREQS_Msk [1/9]

#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

◆ SCB_AIRCR_SYSRESETREQS_Msk [2/9]

#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

◆ SCB_AIRCR_SYSRESETREQS_Msk [3/9]

#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

◆ SCB_AIRCR_SYSRESETREQS_Msk [4/9]

#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

◆ SCB_AIRCR_SYSRESETREQS_Msk [5/9]

#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

◆ SCB_AIRCR_SYSRESETREQS_Msk [6/9]

#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

◆ SCB_AIRCR_SYSRESETREQS_Msk [7/9]

#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

◆ SCB_AIRCR_SYSRESETREQS_Msk [8/9]

#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

◆ SCB_AIRCR_SYSRESETREQS_Msk [9/9]

#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

◆ SCB_AIRCR_SYSRESETREQS_Pos [1/9]

#define SCB_AIRCR_SYSRESETREQS_Pos   3U

SCB AIRCR: SYSRESETREQS Position

◆ SCB_AIRCR_SYSRESETREQS_Pos [2/9]

#define SCB_AIRCR_SYSRESETREQS_Pos   3U

SCB AIRCR: SYSRESETREQS Position

◆ SCB_AIRCR_SYSRESETREQS_Pos [3/9]

#define SCB_AIRCR_SYSRESETREQS_Pos   3U

SCB AIRCR: SYSRESETREQS Position

◆ SCB_AIRCR_SYSRESETREQS_Pos [4/9]

#define SCB_AIRCR_SYSRESETREQS_Pos   3U

SCB AIRCR: SYSRESETREQS Position

◆ SCB_AIRCR_SYSRESETREQS_Pos [5/9]

#define SCB_AIRCR_SYSRESETREQS_Pos   3U

SCB AIRCR: SYSRESETREQS Position

◆ SCB_AIRCR_SYSRESETREQS_Pos [6/9]

#define SCB_AIRCR_SYSRESETREQS_Pos   3U

SCB AIRCR: SYSRESETREQS Position

◆ SCB_AIRCR_SYSRESETREQS_Pos [7/9]

#define SCB_AIRCR_SYSRESETREQS_Pos   3U

SCB AIRCR: SYSRESETREQS Position

◆ SCB_AIRCR_SYSRESETREQS_Pos [8/9]

#define SCB_AIRCR_SYSRESETREQS_Pos   3U

SCB AIRCR: SYSRESETREQS Position

◆ SCB_AIRCR_SYSRESETREQS_Pos [9/9]

#define SCB_AIRCR_SYSRESETREQS_Pos   3U

SCB AIRCR: SYSRESETREQS Position

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [1/17]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [2/17]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [3/17]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [4/17]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [5/17]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [6/17]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [7/17]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [8/17]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [9/17]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [10/17]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [11/17]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [12/17]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [13/17]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [14/17]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [15/17]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [16/17]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [17/17]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [1/17]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [2/17]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [3/17]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [4/17]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [5/17]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [6/17]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [7/17]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [8/17]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [9/17]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [10/17]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [11/17]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [12/17]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [13/17]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [14/17]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [15/17]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [16/17]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [17/17]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

◆ SCB_AIRCR_VECTKEY_Msk [1/17]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

◆ SCB_AIRCR_VECTKEY_Msk [2/17]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

◆ SCB_AIRCR_VECTKEY_Msk [3/17]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

◆ SCB_AIRCR_VECTKEY_Msk [4/17]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

◆ SCB_AIRCR_VECTKEY_Msk [5/17]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

◆ SCB_AIRCR_VECTKEY_Msk [6/17]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

◆ SCB_AIRCR_VECTKEY_Msk [7/17]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

◆ SCB_AIRCR_VECTKEY_Msk [8/17]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

◆ SCB_AIRCR_VECTKEY_Msk [9/17]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

◆ SCB_AIRCR_VECTKEY_Msk [10/17]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

◆ SCB_AIRCR_VECTKEY_Msk [11/17]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

◆ SCB_AIRCR_VECTKEY_Msk [12/17]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

◆ SCB_AIRCR_VECTKEY_Msk [13/17]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

◆ SCB_AIRCR_VECTKEY_Msk [14/17]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

◆ SCB_AIRCR_VECTKEY_Msk [15/17]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

◆ SCB_AIRCR_VECTKEY_Msk [16/17]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

◆ SCB_AIRCR_VECTKEY_Msk [17/17]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

◆ SCB_AIRCR_VECTKEY_Pos [1/17]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

◆ SCB_AIRCR_VECTKEY_Pos [2/17]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

◆ SCB_AIRCR_VECTKEY_Pos [3/17]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

◆ SCB_AIRCR_VECTKEY_Pos [4/17]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

◆ SCB_AIRCR_VECTKEY_Pos [5/17]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

◆ SCB_AIRCR_VECTKEY_Pos [6/17]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

◆ SCB_AIRCR_VECTKEY_Pos [7/17]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

◆ SCB_AIRCR_VECTKEY_Pos [8/17]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

◆ SCB_AIRCR_VECTKEY_Pos [9/17]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

◆ SCB_AIRCR_VECTKEY_Pos [10/17]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

◆ SCB_AIRCR_VECTKEY_Pos [11/17]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

◆ SCB_AIRCR_VECTKEY_Pos [12/17]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

◆ SCB_AIRCR_VECTKEY_Pos [13/17]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

◆ SCB_AIRCR_VECTKEY_Pos [14/17]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

◆ SCB_AIRCR_VECTKEY_Pos [15/17]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

◆ SCB_AIRCR_VECTKEY_Pos [16/17]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

◆ SCB_AIRCR_VECTKEY_Pos [17/17]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

◆ SCB_AIRCR_VECTKEYSTAT_Msk [1/17]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

◆ SCB_AIRCR_VECTKEYSTAT_Msk [2/17]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

◆ SCB_AIRCR_VECTKEYSTAT_Msk [3/17]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

◆ SCB_AIRCR_VECTKEYSTAT_Msk [4/17]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

◆ SCB_AIRCR_VECTKEYSTAT_Msk [5/17]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

◆ SCB_AIRCR_VECTKEYSTAT_Msk [6/17]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

◆ SCB_AIRCR_VECTKEYSTAT_Msk [7/17]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

◆ SCB_AIRCR_VECTKEYSTAT_Msk [8/17]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

◆ SCB_AIRCR_VECTKEYSTAT_Msk [9/17]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

◆ SCB_AIRCR_VECTKEYSTAT_Msk [10/17]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

◆ SCB_AIRCR_VECTKEYSTAT_Msk [11/17]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

◆ SCB_AIRCR_VECTKEYSTAT_Msk [12/17]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

◆ SCB_AIRCR_VECTKEYSTAT_Msk [13/17]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

◆ SCB_AIRCR_VECTKEYSTAT_Msk [14/17]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

◆ SCB_AIRCR_VECTKEYSTAT_Msk [15/17]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

◆ SCB_AIRCR_VECTKEYSTAT_Msk [16/17]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

◆ SCB_AIRCR_VECTKEYSTAT_Msk [17/17]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

◆ SCB_AIRCR_VECTKEYSTAT_Pos [1/17]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

◆ SCB_AIRCR_VECTKEYSTAT_Pos [2/17]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

◆ SCB_AIRCR_VECTKEYSTAT_Pos [3/17]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

◆ SCB_AIRCR_VECTKEYSTAT_Pos [4/17]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

◆ SCB_AIRCR_VECTKEYSTAT_Pos [5/17]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

◆ SCB_AIRCR_VECTKEYSTAT_Pos [6/17]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

◆ SCB_AIRCR_VECTKEYSTAT_Pos [7/17]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

◆ SCB_AIRCR_VECTKEYSTAT_Pos [8/17]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

◆ SCB_AIRCR_VECTKEYSTAT_Pos [9/17]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

◆ SCB_AIRCR_VECTKEYSTAT_Pos [10/17]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

◆ SCB_AIRCR_VECTKEYSTAT_Pos [11/17]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

◆ SCB_AIRCR_VECTKEYSTAT_Pos [12/17]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

◆ SCB_AIRCR_VECTKEYSTAT_Pos [13/17]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

◆ SCB_AIRCR_VECTKEYSTAT_Pos [14/17]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

◆ SCB_AIRCR_VECTKEYSTAT_Pos [15/17]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

◆ SCB_AIRCR_VECTKEYSTAT_Pos [16/17]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

◆ SCB_AIRCR_VECTKEYSTAT_Pos [17/17]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

◆ SCB_AIRCR_VECTRESET_Msk [1/4]

#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

SCB AIRCR: VECTRESET Mask

◆ SCB_AIRCR_VECTRESET_Msk [2/4]

#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

SCB AIRCR: VECTRESET Mask

◆ SCB_AIRCR_VECTRESET_Msk [3/4]

#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

SCB AIRCR: VECTRESET Mask

◆ SCB_AIRCR_VECTRESET_Msk [4/4]

#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

SCB AIRCR: VECTRESET Mask

◆ SCB_AIRCR_VECTRESET_Pos [1/4]

#define SCB_AIRCR_VECTRESET_Pos   0U

SCB AIRCR: VECTRESET Position

◆ SCB_AIRCR_VECTRESET_Pos [2/4]

#define SCB_AIRCR_VECTRESET_Pos   0U

SCB AIRCR: VECTRESET Position

◆ SCB_AIRCR_VECTRESET_Pos [3/4]

#define SCB_AIRCR_VECTRESET_Pos   0U

SCB AIRCR: VECTRESET Position

◆ SCB_AIRCR_VECTRESET_Pos [4/4]

#define SCB_AIRCR_VECTRESET_Pos   0U

SCB AIRCR: VECTRESET Position

◆ SCB_CACR_DCACTIVE_Msk

#define SCB_CACR_DCACTIVE_Msk   (1UL << SCB_CACR_FORCEWT_Pos)

SCB CACR: DCACTIVE Mask

◆ SCB_CACR_DCACTIVE_Pos

#define SCB_CACR_DCACTIVE_Pos   12U

SCB CACR: DCACTIVE Position

◆ SCB_CACR_DCCLEAN_Msk

#define SCB_CACR_DCCLEAN_Msk   (1UL << SCB_CACR_FORCEWT_Pos)

SCB CACR: DCCLEAN Mask

◆ SCB_CACR_DCCLEAN_Pos

#define SCB_CACR_DCCLEAN_Pos   16U

SCB CACR: DCCLEAN Position

◆ SCB_CACR_ECCDIS_Msk

#define SCB_CACR_ECCDIS_Msk   (1UL << SCB_CACR_ECCDIS_Pos)

SCB CACR: ECCDIS Mask

◆ SCB_CACR_ECCDIS_Pos

#define SCB_CACR_ECCDIS_Pos   1U

SCB CACR: ECCDIS Position

◆ SCB_CACR_ECCEN_Msk

#define SCB_CACR_ECCEN_Msk   (1UL << SCB_CACR_ECCEN_Pos)
Deprecated
SCB CACR: ECCEN Mask

◆ SCB_CACR_ECCEN_Pos

#define SCB_CACR_ECCEN_Pos   1U
Deprecated
SCB CACR: ECCEN Position

◆ SCB_CACR_FORCEWT_Msk [1/2]

#define SCB_CACR_FORCEWT_Msk   (1UL << SCB_CACR_FORCEWT_Pos)

SCB CACR: FORCEWT Mask

◆ SCB_CACR_FORCEWT_Msk [2/2]

#define SCB_CACR_FORCEWT_Msk   (1UL << SCB_CACR_FORCEWT_Pos)

SCB CACR: FORCEWT Mask

◆ SCB_CACR_FORCEWT_Pos [1/2]

#define SCB_CACR_FORCEWT_Pos   2U

SCB CACR: FORCEWT Position

◆ SCB_CACR_FORCEWT_Pos [2/2]

#define SCB_CACR_FORCEWT_Pos   2U

SCB CACR: FORCEWT Position

◆ SCB_CACR_ICACTIVE_Msk

#define SCB_CACR_ICACTIVE_Msk   (1UL << SCB_CACR_FORCEWT_Pos)

SCB CACR: ICACTIVE Mask

◆ SCB_CACR_ICACTIVE_Pos

#define SCB_CACR_ICACTIVE_Pos   13U

SCB CACR: ICACTIVE Position

◆ SCB_CACR_SIWT_Msk

#define SCB_CACR_SIWT_Msk   (1UL /*<< SCB_CACR_SIWT_Pos*/)

SCB CACR: SIWT Mask

◆ SCB_CACR_SIWT_Pos

#define SCB_CACR_SIWT_Pos   0U

SCB CACR: SIWT Position

◆ SCB_CCR_BFHFNMIGN_Msk [1/13]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

◆ SCB_CCR_BFHFNMIGN_Msk [2/13]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

◆ SCB_CCR_BFHFNMIGN_Msk [3/13]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

◆ SCB_CCR_BFHFNMIGN_Msk [4/13]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

◆ SCB_CCR_BFHFNMIGN_Msk [5/13]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

◆ SCB_CCR_BFHFNMIGN_Msk [6/13]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

◆ SCB_CCR_BFHFNMIGN_Msk [7/13]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

◆ SCB_CCR_BFHFNMIGN_Msk [8/13]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

◆ SCB_CCR_BFHFNMIGN_Msk [9/13]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

◆ SCB_CCR_BFHFNMIGN_Msk [10/13]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

◆ SCB_CCR_BFHFNMIGN_Msk [11/13]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

◆ SCB_CCR_BFHFNMIGN_Msk [12/13]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

◆ SCB_CCR_BFHFNMIGN_Msk [13/13]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

◆ SCB_CCR_BFHFNMIGN_Pos [1/13]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

◆ SCB_CCR_BFHFNMIGN_Pos [2/13]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

◆ SCB_CCR_BFHFNMIGN_Pos [3/13]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

◆ SCB_CCR_BFHFNMIGN_Pos [4/13]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

◆ SCB_CCR_BFHFNMIGN_Pos [5/13]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

◆ SCB_CCR_BFHFNMIGN_Pos [6/13]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

◆ SCB_CCR_BFHFNMIGN_Pos [7/13]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

◆ SCB_CCR_BFHFNMIGN_Pos [8/13]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

◆ SCB_CCR_BFHFNMIGN_Pos [9/13]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

◆ SCB_CCR_BFHFNMIGN_Pos [10/13]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

◆ SCB_CCR_BFHFNMIGN_Pos [11/13]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

◆ SCB_CCR_BFHFNMIGN_Pos [12/13]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

◆ SCB_CCR_BFHFNMIGN_Pos [13/13]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

◆ SCB_CCR_BP_Msk [1/10]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

SCB CCR: Branch prediction enable bit Mask

◆ SCB_CCR_BP_Msk [2/10]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

SCB CCR: Branch prediction enable bit Mask

◆ SCB_CCR_BP_Msk [3/10]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

SCB CCR: Branch prediction enable bit Mask

◆ SCB_CCR_BP_Msk [4/10]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

SCB CCR: Branch prediction enable bit Mask

◆ SCB_CCR_BP_Msk [5/10]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

SCB CCR: Branch prediction enable bit Mask

◆ SCB_CCR_BP_Msk [6/10]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

SCB CCR: Branch prediction enable bit Mask

◆ SCB_CCR_BP_Msk [7/10]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

SCB CCR: Branch prediction enable bit Mask

◆ SCB_CCR_BP_Msk [8/10]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: Branch prediction enable bit Mask

SCB CCR: BP Mask

◆ SCB_CCR_BP_Msk [9/10]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

◆ SCB_CCR_BP_Msk [10/10]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

◆ SCB_CCR_BP_Pos [1/10]

#define SCB_CCR_BP_Pos   18U

SCB CCR: BP Position

SCB CCR: Branch prediction enable bit Position

◆ SCB_CCR_BP_Pos [2/10]

#define SCB_CCR_BP_Pos   18U

SCB CCR: BP Position

SCB CCR: Branch prediction enable bit Position

◆ SCB_CCR_BP_Pos [3/10]

#define SCB_CCR_BP_Pos   18U

SCB CCR: BP Position

SCB CCR: Branch prediction enable bit Position

◆ SCB_CCR_BP_Pos [4/10]

#define SCB_CCR_BP_Pos   18U

SCB CCR: BP Position

SCB CCR: Branch prediction enable bit Position

◆ SCB_CCR_BP_Pos [5/10]

#define SCB_CCR_BP_Pos   18U

SCB CCR: BP Position

SCB CCR: Branch prediction enable bit Position

◆ SCB_CCR_BP_Pos [6/10]

#define SCB_CCR_BP_Pos   18U

SCB CCR: BP Position

SCB CCR: Branch prediction enable bit Position

◆ SCB_CCR_BP_Pos [7/10]

#define SCB_CCR_BP_Pos   18U

SCB CCR: BP Position

SCB CCR: Branch prediction enable bit Position

◆ SCB_CCR_BP_Pos [8/10]

#define SCB_CCR_BP_Pos   18U

SCB CCR: Branch prediction enable bit Position

SCB CCR: BP Position

◆ SCB_CCR_BP_Pos [9/10]

#define SCB_CCR_BP_Pos   18U

SCB CCR: BP Position

◆ SCB_CCR_BP_Pos [10/10]

#define SCB_CCR_BP_Pos   18U

SCB CCR: BP Position

◆ SCB_CCR_DC_Msk [1/10]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

SCB CCR: Cache enable bit Mask

◆ SCB_CCR_DC_Msk [2/10]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

SCB CCR: Cache enable bit Mask

◆ SCB_CCR_DC_Msk [3/10]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

SCB CCR: Cache enable bit Mask

◆ SCB_CCR_DC_Msk [4/10]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

SCB CCR: Cache enable bit Mask

◆ SCB_CCR_DC_Msk [5/10]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

SCB CCR: Cache enable bit Mask

◆ SCB_CCR_DC_Msk [6/10]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

SCB CCR: Cache enable bit Mask

◆ SCB_CCR_DC_Msk [7/10]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

SCB CCR: Cache enable bit Mask

◆ SCB_CCR_DC_Msk [8/10]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: Cache enable bit Mask

SCB CCR: DC Mask

◆ SCB_CCR_DC_Msk [9/10]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

◆ SCB_CCR_DC_Msk [10/10]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

◆ SCB_CCR_DC_Pos [1/10]

#define SCB_CCR_DC_Pos   16U

SCB CCR: DC Position

SCB CCR: Cache enable bit Position

◆ SCB_CCR_DC_Pos [2/10]

#define SCB_CCR_DC_Pos   16U

SCB CCR: DC Position

SCB CCR: Cache enable bit Position

◆ SCB_CCR_DC_Pos [3/10]

#define SCB_CCR_DC_Pos   16U

SCB CCR: DC Position

SCB CCR: Cache enable bit Position

◆ SCB_CCR_DC_Pos [4/10]

#define SCB_CCR_DC_Pos   16U

SCB CCR: DC Position

SCB CCR: Cache enable bit Position

◆ SCB_CCR_DC_Pos [5/10]

#define SCB_CCR_DC_Pos   16U

SCB CCR: DC Position

SCB CCR: Cache enable bit Position

◆ SCB_CCR_DC_Pos [6/10]

#define SCB_CCR_DC_Pos   16U

SCB CCR: DC Position

SCB CCR: Cache enable bit Position

◆ SCB_CCR_DC_Pos [7/10]

#define SCB_CCR_DC_Pos   16U

SCB CCR: DC Position

SCB CCR: Cache enable bit Position

◆ SCB_CCR_DC_Pos [8/10]

#define SCB_CCR_DC_Pos   16U

SCB CCR: Cache enable bit Position

SCB CCR: DC Position

◆ SCB_CCR_DC_Pos [9/10]

#define SCB_CCR_DC_Pos   16U

SCB CCR: DC Position

◆ SCB_CCR_DC_Pos [10/10]

#define SCB_CCR_DC_Pos   16U

SCB CCR: DC Position

◆ SCB_CCR_DIV_0_TRP_Msk [1/13]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

◆ SCB_CCR_DIV_0_TRP_Msk [2/13]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

◆ SCB_CCR_DIV_0_TRP_Msk [3/13]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

◆ SCB_CCR_DIV_0_TRP_Msk [4/13]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

◆ SCB_CCR_DIV_0_TRP_Msk [5/13]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

◆ SCB_CCR_DIV_0_TRP_Msk [6/13]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

◆ SCB_CCR_DIV_0_TRP_Msk [7/13]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

◆ SCB_CCR_DIV_0_TRP_Msk [8/13]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

◆ SCB_CCR_DIV_0_TRP_Msk [9/13]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

◆ SCB_CCR_DIV_0_TRP_Msk [10/13]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

◆ SCB_CCR_DIV_0_TRP_Msk [11/13]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

◆ SCB_CCR_DIV_0_TRP_Msk [12/13]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

◆ SCB_CCR_DIV_0_TRP_Msk [13/13]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

◆ SCB_CCR_DIV_0_TRP_Pos [1/13]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

◆ SCB_CCR_DIV_0_TRP_Pos [2/13]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

◆ SCB_CCR_DIV_0_TRP_Pos [3/13]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

◆ SCB_CCR_DIV_0_TRP_Pos [4/13]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

◆ SCB_CCR_DIV_0_TRP_Pos [5/13]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

◆ SCB_CCR_DIV_0_TRP_Pos [6/13]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

◆ SCB_CCR_DIV_0_TRP_Pos [7/13]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

◆ SCB_CCR_DIV_0_TRP_Pos [8/13]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

◆ SCB_CCR_DIV_0_TRP_Pos [9/13]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

◆ SCB_CCR_DIV_0_TRP_Pos [10/13]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

◆ SCB_CCR_DIV_0_TRP_Pos [11/13]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

◆ SCB_CCR_DIV_0_TRP_Pos [12/13]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

◆ SCB_CCR_DIV_0_TRP_Pos [13/13]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

◆ SCB_CCR_IC_Msk [1/10]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

SCB CCR: Instruction cache enable bit Mask

◆ SCB_CCR_IC_Msk [2/10]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

SCB CCR: Instruction cache enable bit Mask

◆ SCB_CCR_IC_Msk [3/10]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

SCB CCR: Instruction cache enable bit Mask

◆ SCB_CCR_IC_Msk [4/10]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

SCB CCR: Instruction cache enable bit Mask

◆ SCB_CCR_IC_Msk [5/10]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

SCB CCR: Instruction cache enable bit Mask

◆ SCB_CCR_IC_Msk [6/10]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

SCB CCR: Instruction cache enable bit Mask

◆ SCB_CCR_IC_Msk [7/10]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

SCB CCR: Instruction cache enable bit Mask

◆ SCB_CCR_IC_Msk [8/10]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: Instruction cache enable bit Mask

SCB CCR: IC Mask

◆ SCB_CCR_IC_Msk [9/10]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

◆ SCB_CCR_IC_Msk [10/10]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

◆ SCB_CCR_IC_Pos [1/10]

#define SCB_CCR_IC_Pos   17U

SCB CCR: IC Position

SCB CCR: Instruction cache enable bit Position

◆ SCB_CCR_IC_Pos [2/10]

#define SCB_CCR_IC_Pos   17U

SCB CCR: IC Position

SCB CCR: Instruction cache enable bit Position

◆ SCB_CCR_IC_Pos [3/10]

#define SCB_CCR_IC_Pos   17U

SCB CCR: IC Position

SCB CCR: Instruction cache enable bit Position

◆ SCB_CCR_IC_Pos [4/10]

#define SCB_CCR_IC_Pos   17U

SCB CCR: IC Position

SCB CCR: Instruction cache enable bit Position

◆ SCB_CCR_IC_Pos [5/10]

#define SCB_CCR_IC_Pos   17U

SCB CCR: IC Position

SCB CCR: Instruction cache enable bit Position

◆ SCB_CCR_IC_Pos [6/10]

#define SCB_CCR_IC_Pos   17U

SCB CCR: IC Position

SCB CCR: Instruction cache enable bit Position

◆ SCB_CCR_IC_Pos [7/10]

#define SCB_CCR_IC_Pos   17U

SCB CCR: IC Position

SCB CCR: Instruction cache enable bit Position

◆ SCB_CCR_IC_Pos [8/10]

#define SCB_CCR_IC_Pos   17U

SCB CCR: Instruction cache enable bit Position

SCB CCR: IC Position

◆ SCB_CCR_IC_Pos [9/10]

#define SCB_CCR_IC_Pos   17U

SCB CCR: IC Position

◆ SCB_CCR_IC_Pos [10/10]

#define SCB_CCR_IC_Pos   17U

SCB CCR: IC Position

◆ SCB_CCR_LOB_Msk [1/3]

#define SCB_CCR_LOB_Msk   (1UL << SCB_CCR_LOB_Pos)

SCB CCR: LOB Mask

◆ SCB_CCR_LOB_Msk [2/3]

#define SCB_CCR_LOB_Msk   (1UL << SCB_CCR_LOB_Pos)

SCB CCR: LOB Mask

◆ SCB_CCR_LOB_Msk [3/3]

#define SCB_CCR_LOB_Msk   (1UL << SCB_CCR_LOB_Pos)

SCB CCR: LOB Mask

◆ SCB_CCR_LOB_Pos [1/3]

#define SCB_CCR_LOB_Pos   19U

SCB CCR: LOB Position

◆ SCB_CCR_LOB_Pos [2/3]

#define SCB_CCR_LOB_Pos   19U

SCB CCR: LOB Position

◆ SCB_CCR_LOB_Pos [3/3]

#define SCB_CCR_LOB_Pos   19U

SCB CCR: LOB Position

◆ SCB_CCR_NONBASETHRDENA_Msk [1/4]

#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

SCB CCR: NONBASETHRDENA Mask

◆ SCB_CCR_NONBASETHRDENA_Msk [2/4]

#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

SCB CCR: NONBASETHRDENA Mask

◆ SCB_CCR_NONBASETHRDENA_Msk [3/4]

#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

SCB CCR: NONBASETHRDENA Mask

◆ SCB_CCR_NONBASETHRDENA_Msk [4/4]

#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

SCB CCR: NONBASETHRDENA Mask

◆ SCB_CCR_NONBASETHRDENA_Pos [1/4]

#define SCB_CCR_NONBASETHRDENA_Pos   0U

SCB CCR: NONBASETHRDENA Position

◆ SCB_CCR_NONBASETHRDENA_Pos [2/4]

#define SCB_CCR_NONBASETHRDENA_Pos   0U

SCB CCR: NONBASETHRDENA Position

◆ SCB_CCR_NONBASETHRDENA_Pos [3/4]

#define SCB_CCR_NONBASETHRDENA_Pos   0U

SCB CCR: NONBASETHRDENA Position

◆ SCB_CCR_NONBASETHRDENA_Pos [4/4]

#define SCB_CCR_NONBASETHRDENA_Pos   0U

SCB CCR: NONBASETHRDENA Position

◆ SCB_CCR_STKALIGN_Msk [1/8]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

◆ SCB_CCR_STKALIGN_Msk [2/8]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

◆ SCB_CCR_STKALIGN_Msk [3/8]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

◆ SCB_CCR_STKALIGN_Msk [4/8]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

◆ SCB_CCR_STKALIGN_Msk [5/8]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

◆ SCB_CCR_STKALIGN_Msk [6/8]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

◆ SCB_CCR_STKALIGN_Msk [7/8]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

◆ SCB_CCR_STKALIGN_Msk [8/8]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

◆ SCB_CCR_STKALIGN_Pos [1/8]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

◆ SCB_CCR_STKALIGN_Pos [2/8]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

◆ SCB_CCR_STKALIGN_Pos [3/8]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

◆ SCB_CCR_STKALIGN_Pos [4/8]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

◆ SCB_CCR_STKALIGN_Pos [5/8]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

◆ SCB_CCR_STKALIGN_Pos [6/8]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

◆ SCB_CCR_STKALIGN_Pos [7/8]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

◆ SCB_CCR_STKALIGN_Pos [8/8]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

◆ SCB_CCR_STKOFHFNMIGN_Msk [1/9]

#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

◆ SCB_CCR_STKOFHFNMIGN_Msk [2/9]

#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

◆ SCB_CCR_STKOFHFNMIGN_Msk [3/9]

#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

◆ SCB_CCR_STKOFHFNMIGN_Msk [4/9]

#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

◆ SCB_CCR_STKOFHFNMIGN_Msk [5/9]

#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

◆ SCB_CCR_STKOFHFNMIGN_Msk [6/9]

#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

◆ SCB_CCR_STKOFHFNMIGN_Msk [7/9]

#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

◆ SCB_CCR_STKOFHFNMIGN_Msk [8/9]

#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

◆ SCB_CCR_STKOFHFNMIGN_Msk [9/9]

#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

◆ SCB_CCR_STKOFHFNMIGN_Pos [1/9]

#define SCB_CCR_STKOFHFNMIGN_Pos   10U

SCB CCR: STKOFHFNMIGN Position

◆ SCB_CCR_STKOFHFNMIGN_Pos [2/9]

#define SCB_CCR_STKOFHFNMIGN_Pos   10U

SCB CCR: STKOFHFNMIGN Position

◆ SCB_CCR_STKOFHFNMIGN_Pos [3/9]

#define SCB_CCR_STKOFHFNMIGN_Pos   10U

SCB CCR: STKOFHFNMIGN Position

◆ SCB_CCR_STKOFHFNMIGN_Pos [4/9]

#define SCB_CCR_STKOFHFNMIGN_Pos   10U

SCB CCR: STKOFHFNMIGN Position

◆ SCB_CCR_STKOFHFNMIGN_Pos [5/9]

#define SCB_CCR_STKOFHFNMIGN_Pos   10U

SCB CCR: STKOFHFNMIGN Position

◆ SCB_CCR_STKOFHFNMIGN_Pos [6/9]

#define SCB_CCR_STKOFHFNMIGN_Pos   10U

SCB CCR: STKOFHFNMIGN Position

◆ SCB_CCR_STKOFHFNMIGN_Pos [7/9]

#define SCB_CCR_STKOFHFNMIGN_Pos   10U

SCB CCR: STKOFHFNMIGN Position

◆ SCB_CCR_STKOFHFNMIGN_Pos [8/9]

#define SCB_CCR_STKOFHFNMIGN_Pos   10U

SCB CCR: STKOFHFNMIGN Position

◆ SCB_CCR_STKOFHFNMIGN_Pos [9/9]

#define SCB_CCR_STKOFHFNMIGN_Pos   10U

SCB CCR: STKOFHFNMIGN Position

◆ SCB_CCR_TRD_Msk [1/3]

#define SCB_CCR_TRD_Msk   (1UL << SCB_CCR_TRD_Pos)

SCB CCR: TRD Mask

◆ SCB_CCR_TRD_Msk [2/3]

#define SCB_CCR_TRD_Msk   (1UL << SCB_CCR_TRD_Pos)

SCB CCR: TRD Mask

◆ SCB_CCR_TRD_Msk [3/3]

#define SCB_CCR_TRD_Msk   (1UL << SCB_CCR_TRD_Pos)

SCB CCR: TRD Mask

◆ SCB_CCR_TRD_Pos [1/3]

#define SCB_CCR_TRD_Pos   20U

SCB CCR: TRD Position

◆ SCB_CCR_TRD_Pos [2/3]

#define SCB_CCR_TRD_Pos   20U

SCB CCR: TRD Position

◆ SCB_CCR_TRD_Pos [3/3]

#define SCB_CCR_TRD_Pos   20U

SCB CCR: TRD Position

◆ SCB_CCR_UNALIGN_TRP_Msk [1/17]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

◆ SCB_CCR_UNALIGN_TRP_Msk [2/17]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

◆ SCB_CCR_UNALIGN_TRP_Msk [3/17]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

◆ SCB_CCR_UNALIGN_TRP_Msk [4/17]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

◆ SCB_CCR_UNALIGN_TRP_Msk [5/17]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

◆ SCB_CCR_UNALIGN_TRP_Msk [6/17]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

◆ SCB_CCR_UNALIGN_TRP_Msk [7/17]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

◆ SCB_CCR_UNALIGN_TRP_Msk [8/17]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

◆ SCB_CCR_UNALIGN_TRP_Msk [9/17]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

◆ SCB_CCR_UNALIGN_TRP_Msk [10/17]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

◆ SCB_CCR_UNALIGN_TRP_Msk [11/17]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

◆ SCB_CCR_UNALIGN_TRP_Msk [12/17]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

◆ SCB_CCR_UNALIGN_TRP_Msk [13/17]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

◆ SCB_CCR_UNALIGN_TRP_Msk [14/17]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

◆ SCB_CCR_UNALIGN_TRP_Msk [15/17]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

◆ SCB_CCR_UNALIGN_TRP_Msk [16/17]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

◆ SCB_CCR_UNALIGN_TRP_Msk [17/17]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

◆ SCB_CCR_UNALIGN_TRP_Pos [1/17]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

◆ SCB_CCR_UNALIGN_TRP_Pos [2/17]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

◆ SCB_CCR_UNALIGN_TRP_Pos [3/17]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

◆ SCB_CCR_UNALIGN_TRP_Pos [4/17]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

◆ SCB_CCR_UNALIGN_TRP_Pos [5/17]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

◆ SCB_CCR_UNALIGN_TRP_Pos [6/17]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

◆ SCB_CCR_UNALIGN_TRP_Pos [7/17]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

◆ SCB_CCR_UNALIGN_TRP_Pos [8/17]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

◆ SCB_CCR_UNALIGN_TRP_Pos [9/17]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

◆ SCB_CCR_UNALIGN_TRP_Pos [10/17]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

◆ SCB_CCR_UNALIGN_TRP_Pos [11/17]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

◆ SCB_CCR_UNALIGN_TRP_Pos [12/17]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

◆ SCB_CCR_UNALIGN_TRP_Pos [13/17]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

◆ SCB_CCR_UNALIGN_TRP_Pos [14/17]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

◆ SCB_CCR_UNALIGN_TRP_Pos [15/17]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

◆ SCB_CCR_UNALIGN_TRP_Pos [16/17]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

◆ SCB_CCR_UNALIGN_TRP_Pos [17/17]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

◆ SCB_CCR_USERSETMPEND_Msk [1/13]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

◆ SCB_CCR_USERSETMPEND_Msk [2/13]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

◆ SCB_CCR_USERSETMPEND_Msk [3/13]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

◆ SCB_CCR_USERSETMPEND_Msk [4/13]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

◆ SCB_CCR_USERSETMPEND_Msk [5/13]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

◆ SCB_CCR_USERSETMPEND_Msk [6/13]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

◆ SCB_CCR_USERSETMPEND_Msk [7/13]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

◆ SCB_CCR_USERSETMPEND_Msk [8/13]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

◆ SCB_CCR_USERSETMPEND_Msk [9/13]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

◆ SCB_CCR_USERSETMPEND_Msk [10/13]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

◆ SCB_CCR_USERSETMPEND_Msk [11/13]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

◆ SCB_CCR_USERSETMPEND_Msk [12/13]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

◆ SCB_CCR_USERSETMPEND_Msk [13/13]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

◆ SCB_CCR_USERSETMPEND_Pos [1/13]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

◆ SCB_CCR_USERSETMPEND_Pos [2/13]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

◆ SCB_CCR_USERSETMPEND_Pos [3/13]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

◆ SCB_CCR_USERSETMPEND_Pos [4/13]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

◆ SCB_CCR_USERSETMPEND_Pos [5/13]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

◆ SCB_CCR_USERSETMPEND_Pos [6/13]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

◆ SCB_CCR_USERSETMPEND_Pos [7/13]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

◆ SCB_CCR_USERSETMPEND_Pos [8/13]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

◆ SCB_CCR_USERSETMPEND_Pos [9/13]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

◆ SCB_CCR_USERSETMPEND_Pos [10/13]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

◆ SCB_CCR_USERSETMPEND_Pos [11/13]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

◆ SCB_CCR_USERSETMPEND_Pos [12/13]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

◆ SCB_CCR_USERSETMPEND_Pos [13/13]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

◆ SCB_CCSIDR_ASSOCIATIVITY_Msk [1/8]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

◆ SCB_CCSIDR_ASSOCIATIVITY_Msk [2/8]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

◆ SCB_CCSIDR_ASSOCIATIVITY_Msk [3/8]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

◆ SCB_CCSIDR_ASSOCIATIVITY_Msk [4/8]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

◆ SCB_CCSIDR_ASSOCIATIVITY_Msk [5/8]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

◆ SCB_CCSIDR_ASSOCIATIVITY_Msk [6/8]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

◆ SCB_CCSIDR_ASSOCIATIVITY_Msk [7/8]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

◆ SCB_CCSIDR_ASSOCIATIVITY_Msk [8/8]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

◆ SCB_CCSIDR_ASSOCIATIVITY_Pos [1/8]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U

SCB CCSIDR: Associativity Position

◆ SCB_CCSIDR_ASSOCIATIVITY_Pos [2/8]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U

SCB CCSIDR: Associativity Position

◆ SCB_CCSIDR_ASSOCIATIVITY_Pos [3/8]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U

SCB CCSIDR: Associativity Position

◆ SCB_CCSIDR_ASSOCIATIVITY_Pos [4/8]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U

SCB CCSIDR: Associativity Position

◆ SCB_CCSIDR_ASSOCIATIVITY_Pos [5/8]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U

SCB CCSIDR: Associativity Position

◆ SCB_CCSIDR_ASSOCIATIVITY_Pos [6/8]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U

SCB CCSIDR: Associativity Position

◆ SCB_CCSIDR_ASSOCIATIVITY_Pos [7/8]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U

SCB CCSIDR: Associativity Position

◆ SCB_CCSIDR_ASSOCIATIVITY_Pos [8/8]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U

SCB CCSIDR: Associativity Position

◆ SCB_CCSIDR_LINESIZE_Msk [1/8]

#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

◆ SCB_CCSIDR_LINESIZE_Msk [2/8]

#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

◆ SCB_CCSIDR_LINESIZE_Msk [3/8]

#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

◆ SCB_CCSIDR_LINESIZE_Msk [4/8]

#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

◆ SCB_CCSIDR_LINESIZE_Msk [5/8]

#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

◆ SCB_CCSIDR_LINESIZE_Msk [6/8]

#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

◆ SCB_CCSIDR_LINESIZE_Msk [7/8]

#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

◆ SCB_CCSIDR_LINESIZE_Msk [8/8]

#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

◆ SCB_CCSIDR_LINESIZE_Pos [1/8]

#define SCB_CCSIDR_LINESIZE_Pos   0U

SCB CCSIDR: LineSize Position

◆ SCB_CCSIDR_LINESIZE_Pos [2/8]

#define SCB_CCSIDR_LINESIZE_Pos   0U

SCB CCSIDR: LineSize Position

◆ SCB_CCSIDR_LINESIZE_Pos [3/8]

#define SCB_CCSIDR_LINESIZE_Pos   0U

SCB CCSIDR: LineSize Position

◆ SCB_CCSIDR_LINESIZE_Pos [4/8]

#define SCB_CCSIDR_LINESIZE_Pos   0U

SCB CCSIDR: LineSize Position

◆ SCB_CCSIDR_LINESIZE_Pos [5/8]

#define SCB_CCSIDR_LINESIZE_Pos   0U

SCB CCSIDR: LineSize Position

◆ SCB_CCSIDR_LINESIZE_Pos [6/8]

#define SCB_CCSIDR_LINESIZE_Pos   0U

SCB CCSIDR: LineSize Position

◆ SCB_CCSIDR_LINESIZE_Pos [7/8]

#define SCB_CCSIDR_LINESIZE_Pos   0U

SCB CCSIDR: LineSize Position

◆ SCB_CCSIDR_LINESIZE_Pos [8/8]

#define SCB_CCSIDR_LINESIZE_Pos   0U

SCB CCSIDR: LineSize Position

◆ SCB_CCSIDR_NUMSETS_Msk [1/8]

#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

◆ SCB_CCSIDR_NUMSETS_Msk [2/8]

#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

◆ SCB_CCSIDR_NUMSETS_Msk [3/8]

#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

◆ SCB_CCSIDR_NUMSETS_Msk [4/8]

#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

◆ SCB_CCSIDR_NUMSETS_Msk [5/8]

#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

◆ SCB_CCSIDR_NUMSETS_Msk [6/8]

#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

◆ SCB_CCSIDR_NUMSETS_Msk [7/8]

#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

◆ SCB_CCSIDR_NUMSETS_Msk [8/8]

#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

◆ SCB_CCSIDR_NUMSETS_Pos [1/8]

#define SCB_CCSIDR_NUMSETS_Pos   13U

SCB CCSIDR: NumSets Position

◆ SCB_CCSIDR_NUMSETS_Pos [2/8]

#define SCB_CCSIDR_NUMSETS_Pos   13U

SCB CCSIDR: NumSets Position

◆ SCB_CCSIDR_NUMSETS_Pos [3/8]

#define SCB_CCSIDR_NUMSETS_Pos   13U

SCB CCSIDR: NumSets Position

◆ SCB_CCSIDR_NUMSETS_Pos [4/8]

#define SCB_CCSIDR_NUMSETS_Pos   13U

SCB CCSIDR: NumSets Position

◆ SCB_CCSIDR_NUMSETS_Pos [5/8]

#define SCB_CCSIDR_NUMSETS_Pos   13U

SCB CCSIDR: NumSets Position

◆ SCB_CCSIDR_NUMSETS_Pos [6/8]

#define SCB_CCSIDR_NUMSETS_Pos   13U

SCB CCSIDR: NumSets Position

◆ SCB_CCSIDR_NUMSETS_Pos [7/8]

#define SCB_CCSIDR_NUMSETS_Pos   13U

SCB CCSIDR: NumSets Position

◆ SCB_CCSIDR_NUMSETS_Pos [8/8]

#define SCB_CCSIDR_NUMSETS_Pos   13U

SCB CCSIDR: NumSets Position

◆ SCB_CCSIDR_RA_Msk [1/8]

#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

◆ SCB_CCSIDR_RA_Msk [2/8]

#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

◆ SCB_CCSIDR_RA_Msk [3/8]

#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

◆ SCB_CCSIDR_RA_Msk [4/8]

#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

◆ SCB_CCSIDR_RA_Msk [5/8]

#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

◆ SCB_CCSIDR_RA_Msk [6/8]

#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

◆ SCB_CCSIDR_RA_Msk [7/8]

#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

◆ SCB_CCSIDR_RA_Msk [8/8]

#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

◆ SCB_CCSIDR_RA_Pos [1/8]

#define SCB_CCSIDR_RA_Pos   29U

SCB CCSIDR: RA Position

◆ SCB_CCSIDR_RA_Pos [2/8]

#define SCB_CCSIDR_RA_Pos   29U

SCB CCSIDR: RA Position

◆ SCB_CCSIDR_RA_Pos [3/8]

#define SCB_CCSIDR_RA_Pos   29U

SCB CCSIDR: RA Position

◆ SCB_CCSIDR_RA_Pos [4/8]

#define SCB_CCSIDR_RA_Pos   29U

SCB CCSIDR: RA Position

◆ SCB_CCSIDR_RA_Pos [5/8]

#define SCB_CCSIDR_RA_Pos   29U

SCB CCSIDR: RA Position

◆ SCB_CCSIDR_RA_Pos [6/8]

#define SCB_CCSIDR_RA_Pos   29U

SCB CCSIDR: RA Position

◆ SCB_CCSIDR_RA_Pos [7/8]

#define SCB_CCSIDR_RA_Pos   29U

SCB CCSIDR: RA Position

◆ SCB_CCSIDR_RA_Pos [8/8]

#define SCB_CCSIDR_RA_Pos   29U

SCB CCSIDR: RA Position

◆ SCB_CCSIDR_WA_Msk [1/8]

#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

◆ SCB_CCSIDR_WA_Msk [2/8]

#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

◆ SCB_CCSIDR_WA_Msk [3/8]

#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

◆ SCB_CCSIDR_WA_Msk [4/8]

#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

◆ SCB_CCSIDR_WA_Msk [5/8]

#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

◆ SCB_CCSIDR_WA_Msk [6/8]

#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

◆ SCB_CCSIDR_WA_Msk [7/8]

#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

◆ SCB_CCSIDR_WA_Msk [8/8]

#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

◆ SCB_CCSIDR_WA_Pos [1/8]

#define SCB_CCSIDR_WA_Pos   28U

SCB CCSIDR: WA Position

◆ SCB_CCSIDR_WA_Pos [2/8]

#define SCB_CCSIDR_WA_Pos   28U

SCB CCSIDR: WA Position

◆ SCB_CCSIDR_WA_Pos [3/8]

#define SCB_CCSIDR_WA_Pos   28U

SCB CCSIDR: WA Position

◆ SCB_CCSIDR_WA_Pos [4/8]

#define SCB_CCSIDR_WA_Pos   28U

SCB CCSIDR: WA Position

◆ SCB_CCSIDR_WA_Pos [5/8]

#define SCB_CCSIDR_WA_Pos   28U

SCB CCSIDR: WA Position

◆ SCB_CCSIDR_WA_Pos [6/8]

#define SCB_CCSIDR_WA_Pos   28U

SCB CCSIDR: WA Position

◆ SCB_CCSIDR_WA_Pos [7/8]

#define SCB_CCSIDR_WA_Pos   28U

SCB CCSIDR: WA Position

◆ SCB_CCSIDR_WA_Pos [8/8]

#define SCB_CCSIDR_WA_Pos   28U

SCB CCSIDR: WA Position

◆ SCB_CCSIDR_WB_Msk [1/8]

#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

◆ SCB_CCSIDR_WB_Msk [2/8]

#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

◆ SCB_CCSIDR_WB_Msk [3/8]

#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

◆ SCB_CCSIDR_WB_Msk [4/8]

#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

◆ SCB_CCSIDR_WB_Msk [5/8]

#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

◆ SCB_CCSIDR_WB_Msk [6/8]

#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

◆ SCB_CCSIDR_WB_Msk [7/8]

#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

◆ SCB_CCSIDR_WB_Msk [8/8]

#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

◆ SCB_CCSIDR_WB_Pos [1/8]

#define SCB_CCSIDR_WB_Pos   30U

SCB CCSIDR: WB Position

◆ SCB_CCSIDR_WB_Pos [2/8]

#define SCB_CCSIDR_WB_Pos   30U

SCB CCSIDR: WB Position

◆ SCB_CCSIDR_WB_Pos [3/8]

#define SCB_CCSIDR_WB_Pos   30U

SCB CCSIDR: WB Position

◆ SCB_CCSIDR_WB_Pos [4/8]

#define SCB_CCSIDR_WB_Pos   30U

SCB CCSIDR: WB Position

◆ SCB_CCSIDR_WB_Pos [5/8]

#define SCB_CCSIDR_WB_Pos   30U

SCB CCSIDR: WB Position

◆ SCB_CCSIDR_WB_Pos [6/8]

#define SCB_CCSIDR_WB_Pos   30U

SCB CCSIDR: WB Position

◆ SCB_CCSIDR_WB_Pos [7/8]

#define SCB_CCSIDR_WB_Pos   30U

SCB CCSIDR: WB Position

◆ SCB_CCSIDR_WB_Pos [8/8]

#define SCB_CCSIDR_WB_Pos   30U

SCB CCSIDR: WB Position

◆ SCB_CCSIDR_WT_Msk [1/8]

#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

◆ SCB_CCSIDR_WT_Msk [2/8]

#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

◆ SCB_CCSIDR_WT_Msk [3/8]

#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

◆ SCB_CCSIDR_WT_Msk [4/8]

#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

◆ SCB_CCSIDR_WT_Msk [5/8]

#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

◆ SCB_CCSIDR_WT_Msk [6/8]

#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

◆ SCB_CCSIDR_WT_Msk [7/8]

#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

◆ SCB_CCSIDR_WT_Msk [8/8]

#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

◆ SCB_CCSIDR_WT_Pos [1/8]

#define SCB_CCSIDR_WT_Pos   31U

SCB CCSIDR: WT Position

◆ SCB_CCSIDR_WT_Pos [2/8]

#define SCB_CCSIDR_WT_Pos   31U

SCB CCSIDR: WT Position

◆ SCB_CCSIDR_WT_Pos [3/8]

#define SCB_CCSIDR_WT_Pos   31U

SCB CCSIDR: WT Position

◆ SCB_CCSIDR_WT_Pos [4/8]

#define SCB_CCSIDR_WT_Pos   31U

SCB CCSIDR: WT Position

◆ SCB_CCSIDR_WT_Pos [5/8]

#define SCB_CCSIDR_WT_Pos   31U

SCB CCSIDR: WT Position

◆ SCB_CCSIDR_WT_Pos [6/8]

#define SCB_CCSIDR_WT_Pos   31U

SCB CCSIDR: WT Position

◆ SCB_CCSIDR_WT_Pos [7/8]

#define SCB_CCSIDR_WT_Pos   31U

SCB CCSIDR: WT Position

◆ SCB_CCSIDR_WT_Pos [8/8]

#define SCB_CCSIDR_WT_Pos   31U

SCB CCSIDR: WT Position

◆ SCB_CFSR_BFARVALID_Msk [1/11]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

◆ SCB_CFSR_BFARVALID_Msk [2/11]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

◆ SCB_CFSR_BFARVALID_Msk [3/11]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

◆ SCB_CFSR_BFARVALID_Msk [4/11]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

◆ SCB_CFSR_BFARVALID_Msk [5/11]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

◆ SCB_CFSR_BFARVALID_Msk [6/11]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

◆ SCB_CFSR_BFARVALID_Msk [7/11]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

◆ SCB_CFSR_BFARVALID_Msk [8/11]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

◆ SCB_CFSR_BFARVALID_Msk [9/11]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

◆ SCB_CFSR_BFARVALID_Msk [10/11]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

◆ SCB_CFSR_BFARVALID_Msk [11/11]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

◆ SCB_CFSR_BFARVALID_Pos [1/11]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

◆ SCB_CFSR_BFARVALID_Pos [2/11]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

◆ SCB_CFSR_BFARVALID_Pos [3/11]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

◆ SCB_CFSR_BFARVALID_Pos [4/11]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

◆ SCB_CFSR_BFARVALID_Pos [5/11]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

◆ SCB_CFSR_BFARVALID_Pos [6/11]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

◆ SCB_CFSR_BFARVALID_Pos [7/11]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

◆ SCB_CFSR_BFARVALID_Pos [8/11]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

◆ SCB_CFSR_BFARVALID_Pos [9/11]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

◆ SCB_CFSR_BFARVALID_Pos [10/11]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

◆ SCB_CFSR_BFARVALID_Pos [11/11]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

◆ SCB_CFSR_BUSFAULTSR_Msk [1/11]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

◆ SCB_CFSR_BUSFAULTSR_Msk [2/11]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

◆ SCB_CFSR_BUSFAULTSR_Msk [3/11]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

◆ SCB_CFSR_BUSFAULTSR_Msk [4/11]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

◆ SCB_CFSR_BUSFAULTSR_Msk [5/11]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

◆ SCB_CFSR_BUSFAULTSR_Msk [6/11]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

◆ SCB_CFSR_BUSFAULTSR_Msk [7/11]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

◆ SCB_CFSR_BUSFAULTSR_Msk [8/11]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

◆ SCB_CFSR_BUSFAULTSR_Msk [9/11]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

◆ SCB_CFSR_BUSFAULTSR_Msk [10/11]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

◆ SCB_CFSR_BUSFAULTSR_Msk [11/11]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

◆ SCB_CFSR_BUSFAULTSR_Pos [1/11]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

◆ SCB_CFSR_BUSFAULTSR_Pos [2/11]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

◆ SCB_CFSR_BUSFAULTSR_Pos [3/11]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

◆ SCB_CFSR_BUSFAULTSR_Pos [4/11]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

◆ SCB_CFSR_BUSFAULTSR_Pos [5/11]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

◆ SCB_CFSR_BUSFAULTSR_Pos [6/11]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

◆ SCB_CFSR_BUSFAULTSR_Pos [7/11]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

◆ SCB_CFSR_BUSFAULTSR_Pos [8/11]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

◆ SCB_CFSR_BUSFAULTSR_Pos [9/11]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

◆ SCB_CFSR_BUSFAULTSR_Pos [10/11]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

◆ SCB_CFSR_BUSFAULTSR_Pos [11/11]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

◆ SCB_CFSR_DACCVIOL_Msk [1/11]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

◆ SCB_CFSR_DACCVIOL_Msk [2/11]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

◆ SCB_CFSR_DACCVIOL_Msk [3/11]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

◆ SCB_CFSR_DACCVIOL_Msk [4/11]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

◆ SCB_CFSR_DACCVIOL_Msk [5/11]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

◆ SCB_CFSR_DACCVIOL_Msk [6/11]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

◆ SCB_CFSR_DACCVIOL_Msk [7/11]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

◆ SCB_CFSR_DACCVIOL_Msk [8/11]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

◆ SCB_CFSR_DACCVIOL_Msk [9/11]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

◆ SCB_CFSR_DACCVIOL_Msk [10/11]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

◆ SCB_CFSR_DACCVIOL_Msk [11/11]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

◆ SCB_CFSR_DACCVIOL_Pos [1/11]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

◆ SCB_CFSR_DACCVIOL_Pos [2/11]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

◆ SCB_CFSR_DACCVIOL_Pos [3/11]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

◆ SCB_CFSR_DACCVIOL_Pos [4/11]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

◆ SCB_CFSR_DACCVIOL_Pos [5/11]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

◆ SCB_CFSR_DACCVIOL_Pos [6/11]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

◆ SCB_CFSR_DACCVIOL_Pos [7/11]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

◆ SCB_CFSR_DACCVIOL_Pos [8/11]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

◆ SCB_CFSR_DACCVIOL_Pos [9/11]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

◆ SCB_CFSR_DACCVIOL_Pos [10/11]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

◆ SCB_CFSR_DACCVIOL_Pos [11/11]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

◆ SCB_CFSR_DIVBYZERO_Msk [1/11]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

◆ SCB_CFSR_DIVBYZERO_Msk [2/11]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

◆ SCB_CFSR_DIVBYZERO_Msk [3/11]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

◆ SCB_CFSR_DIVBYZERO_Msk [4/11]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

◆ SCB_CFSR_DIVBYZERO_Msk [5/11]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

◆ SCB_CFSR_DIVBYZERO_Msk [6/11]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

◆ SCB_CFSR_DIVBYZERO_Msk [7/11]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

◆ SCB_CFSR_DIVBYZERO_Msk [8/11]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

◆ SCB_CFSR_DIVBYZERO_Msk [9/11]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

◆ SCB_CFSR_DIVBYZERO_Msk [10/11]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

◆ SCB_CFSR_DIVBYZERO_Msk [11/11]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

◆ SCB_CFSR_DIVBYZERO_Pos [1/11]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

◆ SCB_CFSR_DIVBYZERO_Pos [2/11]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

◆ SCB_CFSR_DIVBYZERO_Pos [3/11]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

◆ SCB_CFSR_DIVBYZERO_Pos [4/11]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

◆ SCB_CFSR_DIVBYZERO_Pos [5/11]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

◆ SCB_CFSR_DIVBYZERO_Pos [6/11]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

◆ SCB_CFSR_DIVBYZERO_Pos [7/11]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

◆ SCB_CFSR_DIVBYZERO_Pos [8/11]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

◆ SCB_CFSR_DIVBYZERO_Pos [9/11]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

◆ SCB_CFSR_DIVBYZERO_Pos [10/11]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

◆ SCB_CFSR_DIVBYZERO_Pos [11/11]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

◆ SCB_CFSR_IACCVIOL_Msk [1/11]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

◆ SCB_CFSR_IACCVIOL_Msk [2/11]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

◆ SCB_CFSR_IACCVIOL_Msk [3/11]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

◆ SCB_CFSR_IACCVIOL_Msk [4/11]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

◆ SCB_CFSR_IACCVIOL_Msk [5/11]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

◆ SCB_CFSR_IACCVIOL_Msk [6/11]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

◆ SCB_CFSR_IACCVIOL_Msk [7/11]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

◆ SCB_CFSR_IACCVIOL_Msk [8/11]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

◆ SCB_CFSR_IACCVIOL_Msk [9/11]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

◆ SCB_CFSR_IACCVIOL_Msk [10/11]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

◆ SCB_CFSR_IACCVIOL_Msk [11/11]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

◆ SCB_CFSR_IACCVIOL_Pos [1/11]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

◆ SCB_CFSR_IACCVIOL_Pos [2/11]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

◆ SCB_CFSR_IACCVIOL_Pos [3/11]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

◆ SCB_CFSR_IACCVIOL_Pos [4/11]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

◆ SCB_CFSR_IACCVIOL_Pos [5/11]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

◆ SCB_CFSR_IACCVIOL_Pos [6/11]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

◆ SCB_CFSR_IACCVIOL_Pos [7/11]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

◆ SCB_CFSR_IACCVIOL_Pos [8/11]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

◆ SCB_CFSR_IACCVIOL_Pos [9/11]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

◆ SCB_CFSR_IACCVIOL_Pos [10/11]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

◆ SCB_CFSR_IACCVIOL_Pos [11/11]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

◆ SCB_CFSR_IBUSERR_Msk [1/11]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

◆ SCB_CFSR_IBUSERR_Msk [2/11]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

◆ SCB_CFSR_IBUSERR_Msk [3/11]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

◆ SCB_CFSR_IBUSERR_Msk [4/11]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

◆ SCB_CFSR_IBUSERR_Msk [5/11]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

◆ SCB_CFSR_IBUSERR_Msk [6/11]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

◆ SCB_CFSR_IBUSERR_Msk [7/11]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

◆ SCB_CFSR_IBUSERR_Msk [8/11]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

◆ SCB_CFSR_IBUSERR_Msk [9/11]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

◆ SCB_CFSR_IBUSERR_Msk [10/11]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

◆ SCB_CFSR_IBUSERR_Msk [11/11]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

◆ SCB_CFSR_IBUSERR_Pos [1/11]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

◆ SCB_CFSR_IBUSERR_Pos [2/11]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

◆ SCB_CFSR_IBUSERR_Pos [3/11]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

◆ SCB_CFSR_IBUSERR_Pos [4/11]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

◆ SCB_CFSR_IBUSERR_Pos [5/11]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

◆ SCB_CFSR_IBUSERR_Pos [6/11]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

◆ SCB_CFSR_IBUSERR_Pos [7/11]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

◆ SCB_CFSR_IBUSERR_Pos [8/11]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

◆ SCB_CFSR_IBUSERR_Pos [9/11]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

◆ SCB_CFSR_IBUSERR_Pos [10/11]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

◆ SCB_CFSR_IBUSERR_Pos [11/11]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

◆ SCB_CFSR_IMPRECISERR_Msk [1/11]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

◆ SCB_CFSR_IMPRECISERR_Msk [2/11]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

◆ SCB_CFSR_IMPRECISERR_Msk [3/11]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

◆ SCB_CFSR_IMPRECISERR_Msk [4/11]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

◆ SCB_CFSR_IMPRECISERR_Msk [5/11]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

◆ SCB_CFSR_IMPRECISERR_Msk [6/11]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

◆ SCB_CFSR_IMPRECISERR_Msk [7/11]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

◆ SCB_CFSR_IMPRECISERR_Msk [8/11]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

◆ SCB_CFSR_IMPRECISERR_Msk [9/11]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

◆ SCB_CFSR_IMPRECISERR_Msk [10/11]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

◆ SCB_CFSR_IMPRECISERR_Msk [11/11]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

◆ SCB_CFSR_IMPRECISERR_Pos [1/11]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

◆ SCB_CFSR_IMPRECISERR_Pos [2/11]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

◆ SCB_CFSR_IMPRECISERR_Pos [3/11]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

◆ SCB_CFSR_IMPRECISERR_Pos [4/11]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

◆ SCB_CFSR_IMPRECISERR_Pos [5/11]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

◆ SCB_CFSR_IMPRECISERR_Pos [6/11]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

◆ SCB_CFSR_IMPRECISERR_Pos [7/11]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

◆ SCB_CFSR_IMPRECISERR_Pos [8/11]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

◆ SCB_CFSR_IMPRECISERR_Pos [9/11]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

◆ SCB_CFSR_IMPRECISERR_Pos [10/11]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

◆ SCB_CFSR_IMPRECISERR_Pos [11/11]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

◆ SCB_CFSR_INVPC_Msk [1/11]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

◆ SCB_CFSR_INVPC_Msk [2/11]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

◆ SCB_CFSR_INVPC_Msk [3/11]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

◆ SCB_CFSR_INVPC_Msk [4/11]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

◆ SCB_CFSR_INVPC_Msk [5/11]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

◆ SCB_CFSR_INVPC_Msk [6/11]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

◆ SCB_CFSR_INVPC_Msk [7/11]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

◆ SCB_CFSR_INVPC_Msk [8/11]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

◆ SCB_CFSR_INVPC_Msk [9/11]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

◆ SCB_CFSR_INVPC_Msk [10/11]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

◆ SCB_CFSR_INVPC_Msk [11/11]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

◆ SCB_CFSR_INVPC_Pos [1/11]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

◆ SCB_CFSR_INVPC_Pos [2/11]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

◆ SCB_CFSR_INVPC_Pos [3/11]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

◆ SCB_CFSR_INVPC_Pos [4/11]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

◆ SCB_CFSR_INVPC_Pos [5/11]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

◆ SCB_CFSR_INVPC_Pos [6/11]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

◆ SCB_CFSR_INVPC_Pos [7/11]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

◆ SCB_CFSR_INVPC_Pos [8/11]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

◆ SCB_CFSR_INVPC_Pos [9/11]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

◆ SCB_CFSR_INVPC_Pos [10/11]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

◆ SCB_CFSR_INVPC_Pos [11/11]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

◆ SCB_CFSR_INVSTATE_Msk [1/11]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

◆ SCB_CFSR_INVSTATE_Msk [2/11]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

◆ SCB_CFSR_INVSTATE_Msk [3/11]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

◆ SCB_CFSR_INVSTATE_Msk [4/11]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

◆ SCB_CFSR_INVSTATE_Msk [5/11]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

◆ SCB_CFSR_INVSTATE_Msk [6/11]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

◆ SCB_CFSR_INVSTATE_Msk [7/11]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

◆ SCB_CFSR_INVSTATE_Msk [8/11]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

◆ SCB_CFSR_INVSTATE_Msk [9/11]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

◆ SCB_CFSR_INVSTATE_Msk [10/11]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

◆ SCB_CFSR_INVSTATE_Msk [11/11]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

◆ SCB_CFSR_INVSTATE_Pos [1/11]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

◆ SCB_CFSR_INVSTATE_Pos [2/11]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

◆ SCB_CFSR_INVSTATE_Pos [3/11]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

◆ SCB_CFSR_INVSTATE_Pos [4/11]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

◆ SCB_CFSR_INVSTATE_Pos [5/11]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

◆ SCB_CFSR_INVSTATE_Pos [6/11]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

◆ SCB_CFSR_INVSTATE_Pos [7/11]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

◆ SCB_CFSR_INVSTATE_Pos [8/11]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

◆ SCB_CFSR_INVSTATE_Pos [9/11]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

◆ SCB_CFSR_INVSTATE_Pos [10/11]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

◆ SCB_CFSR_INVSTATE_Pos [11/11]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

◆ SCB_CFSR_LSPERR_Msk [1/9]

#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

◆ SCB_CFSR_LSPERR_Msk [2/9]

#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

◆ SCB_CFSR_LSPERR_Msk [3/9]

#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

◆ SCB_CFSR_LSPERR_Msk [4/9]

#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

◆ SCB_CFSR_LSPERR_Msk [5/9]

#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

◆ SCB_CFSR_LSPERR_Msk [6/9]

#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

◆ SCB_CFSR_LSPERR_Msk [7/9]

#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

◆ SCB_CFSR_LSPERR_Msk [8/9]

#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

◆ SCB_CFSR_LSPERR_Msk [9/9]

#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

◆ SCB_CFSR_LSPERR_Pos [1/9]

#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

◆ SCB_CFSR_LSPERR_Pos [2/9]

#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

◆ SCB_CFSR_LSPERR_Pos [3/9]

#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

◆ SCB_CFSR_LSPERR_Pos [4/9]

#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

◆ SCB_CFSR_LSPERR_Pos [5/9]

#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

◆ SCB_CFSR_LSPERR_Pos [6/9]

#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

◆ SCB_CFSR_LSPERR_Pos [7/9]

#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

◆ SCB_CFSR_LSPERR_Pos [8/9]

#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

◆ SCB_CFSR_LSPERR_Pos [9/9]

#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

◆ SCB_CFSR_MEMFAULTSR_Msk [1/11]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

◆ SCB_CFSR_MEMFAULTSR_Msk [2/11]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

◆ SCB_CFSR_MEMFAULTSR_Msk [3/11]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

◆ SCB_CFSR_MEMFAULTSR_Msk [4/11]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

◆ SCB_CFSR_MEMFAULTSR_Msk [5/11]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

◆ SCB_CFSR_MEMFAULTSR_Msk [6/11]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

◆ SCB_CFSR_MEMFAULTSR_Msk [7/11]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

◆ SCB_CFSR_MEMFAULTSR_Msk [8/11]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

◆ SCB_CFSR_MEMFAULTSR_Msk [9/11]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

◆ SCB_CFSR_MEMFAULTSR_Msk [10/11]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

◆ SCB_CFSR_MEMFAULTSR_Msk [11/11]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

◆ SCB_CFSR_MEMFAULTSR_Pos [1/11]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

◆ SCB_CFSR_MEMFAULTSR_Pos [2/11]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

◆ SCB_CFSR_MEMFAULTSR_Pos [3/11]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

◆ SCB_CFSR_MEMFAULTSR_Pos [4/11]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

◆ SCB_CFSR_MEMFAULTSR_Pos [5/11]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

◆ SCB_CFSR_MEMFAULTSR_Pos [6/11]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

◆ SCB_CFSR_MEMFAULTSR_Pos [7/11]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

◆ SCB_CFSR_MEMFAULTSR_Pos [8/11]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

◆ SCB_CFSR_MEMFAULTSR_Pos [9/11]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

◆ SCB_CFSR_MEMFAULTSR_Pos [10/11]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

◆ SCB_CFSR_MEMFAULTSR_Pos [11/11]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

◆ SCB_CFSR_MLSPERR_Msk [1/9]

#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

◆ SCB_CFSR_MLSPERR_Msk [2/9]

#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

◆ SCB_CFSR_MLSPERR_Msk [3/9]

#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

◆ SCB_CFSR_MLSPERR_Msk [4/9]

#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

◆ SCB_CFSR_MLSPERR_Msk [5/9]

#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

◆ SCB_CFSR_MLSPERR_Msk [6/9]

#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

◆ SCB_CFSR_MLSPERR_Msk [7/9]

#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

◆ SCB_CFSR_MLSPERR_Msk [8/9]

#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

◆ SCB_CFSR_MLSPERR_Msk [9/9]

#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

◆ SCB_CFSR_MLSPERR_Pos [1/9]

#define SCB_CFSR_MLSPERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

◆ SCB_CFSR_MLSPERR_Pos [2/9]

#define SCB_CFSR_MLSPERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

◆ SCB_CFSR_MLSPERR_Pos [3/9]

#define SCB_CFSR_MLSPERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

◆ SCB_CFSR_MLSPERR_Pos [4/9]

#define SCB_CFSR_MLSPERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

◆ SCB_CFSR_MLSPERR_Pos [5/9]

#define SCB_CFSR_MLSPERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

◆ SCB_CFSR_MLSPERR_Pos [6/9]

#define SCB_CFSR_MLSPERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

◆ SCB_CFSR_MLSPERR_Pos [7/9]

#define SCB_CFSR_MLSPERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

◆ SCB_CFSR_MLSPERR_Pos [8/9]

#define SCB_CFSR_MLSPERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

◆ SCB_CFSR_MLSPERR_Pos [9/9]

#define SCB_CFSR_MLSPERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

◆ SCB_CFSR_MMARVALID_Msk [1/11]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

◆ SCB_CFSR_MMARVALID_Msk [2/11]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

◆ SCB_CFSR_MMARVALID_Msk [3/11]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

◆ SCB_CFSR_MMARVALID_Msk [4/11]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

◆ SCB_CFSR_MMARVALID_Msk [5/11]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

◆ SCB_CFSR_MMARVALID_Msk [6/11]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

◆ SCB_CFSR_MMARVALID_Msk [7/11]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

◆ SCB_CFSR_MMARVALID_Msk [8/11]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

◆ SCB_CFSR_MMARVALID_Msk [9/11]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

◆ SCB_CFSR_MMARVALID_Msk [10/11]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

◆ SCB_CFSR_MMARVALID_Msk [11/11]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

◆ SCB_CFSR_MMARVALID_Pos [1/11]

#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

◆ SCB_CFSR_MMARVALID_Pos [2/11]

#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

◆ SCB_CFSR_MMARVALID_Pos [3/11]

#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

◆ SCB_CFSR_MMARVALID_Pos [4/11]

#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

◆ SCB_CFSR_MMARVALID_Pos [5/11]

#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

◆ SCB_CFSR_MMARVALID_Pos [6/11]

#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

◆ SCB_CFSR_MMARVALID_Pos [7/11]

#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

◆ SCB_CFSR_MMARVALID_Pos [8/11]

#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

◆ SCB_CFSR_MMARVALID_Pos [9/11]

#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

◆ SCB_CFSR_MMARVALID_Pos [10/11]

#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

◆ SCB_CFSR_MMARVALID_Pos [11/11]

#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

◆ SCB_CFSR_MSTKERR_Msk [1/11]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

◆ SCB_CFSR_MSTKERR_Msk [2/11]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

◆ SCB_CFSR_MSTKERR_Msk [3/11]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

◆ SCB_CFSR_MSTKERR_Msk [4/11]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

◆ SCB_CFSR_MSTKERR_Msk [5/11]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

◆ SCB_CFSR_MSTKERR_Msk [6/11]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

◆ SCB_CFSR_MSTKERR_Msk [7/11]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

◆ SCB_CFSR_MSTKERR_Msk [8/11]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

◆ SCB_CFSR_MSTKERR_Msk [9/11]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

◆ SCB_CFSR_MSTKERR_Msk [10/11]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

◆ SCB_CFSR_MSTKERR_Msk [11/11]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

◆ SCB_CFSR_MSTKERR_Pos [1/11]

#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

◆ SCB_CFSR_MSTKERR_Pos [2/11]

#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

◆ SCB_CFSR_MSTKERR_Pos [3/11]

#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

◆ SCB_CFSR_MSTKERR_Pos [4/11]

#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

◆ SCB_CFSR_MSTKERR_Pos [5/11]

#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

◆ SCB_CFSR_MSTKERR_Pos [6/11]

#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

◆ SCB_CFSR_MSTKERR_Pos [7/11]

#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

◆ SCB_CFSR_MSTKERR_Pos [8/11]

#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

◆ SCB_CFSR_MSTKERR_Pos [9/11]

#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

◆ SCB_CFSR_MSTKERR_Pos [10/11]

#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

◆ SCB_CFSR_MSTKERR_Pos [11/11]

#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

◆ SCB_CFSR_MUNSTKERR_Msk [1/11]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

◆ SCB_CFSR_MUNSTKERR_Msk [2/11]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

◆ SCB_CFSR_MUNSTKERR_Msk [3/11]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

◆ SCB_CFSR_MUNSTKERR_Msk [4/11]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

◆ SCB_CFSR_MUNSTKERR_Msk [5/11]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

◆ SCB_CFSR_MUNSTKERR_Msk [6/11]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

◆ SCB_CFSR_MUNSTKERR_Msk [7/11]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

◆ SCB_CFSR_MUNSTKERR_Msk [8/11]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

◆ SCB_CFSR_MUNSTKERR_Msk [9/11]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

◆ SCB_CFSR_MUNSTKERR_Msk [10/11]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

◆ SCB_CFSR_MUNSTKERR_Msk [11/11]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

◆ SCB_CFSR_MUNSTKERR_Pos [1/11]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

◆ SCB_CFSR_MUNSTKERR_Pos [2/11]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

◆ SCB_CFSR_MUNSTKERR_Pos [3/11]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

◆ SCB_CFSR_MUNSTKERR_Pos [4/11]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

◆ SCB_CFSR_MUNSTKERR_Pos [5/11]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

◆ SCB_CFSR_MUNSTKERR_Pos [6/11]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

◆ SCB_CFSR_MUNSTKERR_Pos [7/11]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

◆ SCB_CFSR_MUNSTKERR_Pos [8/11]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

◆ SCB_CFSR_MUNSTKERR_Pos [9/11]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

◆ SCB_CFSR_MUNSTKERR_Pos [10/11]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

◆ SCB_CFSR_MUNSTKERR_Pos [11/11]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

◆ SCB_CFSR_NOCP_Msk [1/11]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

◆ SCB_CFSR_NOCP_Msk [2/11]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

◆ SCB_CFSR_NOCP_Msk [3/11]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

◆ SCB_CFSR_NOCP_Msk [4/11]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

◆ SCB_CFSR_NOCP_Msk [5/11]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

◆ SCB_CFSR_NOCP_Msk [6/11]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

◆ SCB_CFSR_NOCP_Msk [7/11]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

◆ SCB_CFSR_NOCP_Msk [8/11]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

◆ SCB_CFSR_NOCP_Msk [9/11]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

◆ SCB_CFSR_NOCP_Msk [10/11]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

◆ SCB_CFSR_NOCP_Msk [11/11]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

◆ SCB_CFSR_NOCP_Pos [1/11]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

◆ SCB_CFSR_NOCP_Pos [2/11]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

◆ SCB_CFSR_NOCP_Pos [3/11]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

◆ SCB_CFSR_NOCP_Pos [4/11]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

◆ SCB_CFSR_NOCP_Pos [5/11]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

◆ SCB_CFSR_NOCP_Pos [6/11]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

◆ SCB_CFSR_NOCP_Pos [7/11]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

◆ SCB_CFSR_NOCP_Pos [8/11]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

◆ SCB_CFSR_NOCP_Pos [9/11]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

◆ SCB_CFSR_NOCP_Pos [10/11]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

◆ SCB_CFSR_NOCP_Pos [11/11]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

◆ SCB_CFSR_PRECISERR_Msk [1/11]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

◆ SCB_CFSR_PRECISERR_Msk [2/11]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

◆ SCB_CFSR_PRECISERR_Msk [3/11]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

◆ SCB_CFSR_PRECISERR_Msk [4/11]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

◆ SCB_CFSR_PRECISERR_Msk [5/11]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

◆ SCB_CFSR_PRECISERR_Msk [6/11]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

◆ SCB_CFSR_PRECISERR_Msk [7/11]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

◆ SCB_CFSR_PRECISERR_Msk [8/11]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

◆ SCB_CFSR_PRECISERR_Msk [9/11]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

◆ SCB_CFSR_PRECISERR_Msk [10/11]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

◆ SCB_CFSR_PRECISERR_Msk [11/11]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

◆ SCB_CFSR_PRECISERR_Pos [1/11]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

◆ SCB_CFSR_PRECISERR_Pos [2/11]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

◆ SCB_CFSR_PRECISERR_Pos [3/11]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

◆ SCB_CFSR_PRECISERR_Pos [4/11]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

◆ SCB_CFSR_PRECISERR_Pos [5/11]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

◆ SCB_CFSR_PRECISERR_Pos [6/11]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

◆ SCB_CFSR_PRECISERR_Pos [7/11]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

◆ SCB_CFSR_PRECISERR_Pos [8/11]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

◆ SCB_CFSR_PRECISERR_Pos [9/11]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

◆ SCB_CFSR_PRECISERR_Pos [10/11]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

◆ SCB_CFSR_PRECISERR_Pos [11/11]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

◆ SCB_CFSR_STKERR_Msk [1/11]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

◆ SCB_CFSR_STKERR_Msk [2/11]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

◆ SCB_CFSR_STKERR_Msk [3/11]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

◆ SCB_CFSR_STKERR_Msk [4/11]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

◆ SCB_CFSR_STKERR_Msk [5/11]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

◆ SCB_CFSR_STKERR_Msk [6/11]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

◆ SCB_CFSR_STKERR_Msk [7/11]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

◆ SCB_CFSR_STKERR_Msk [8/11]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

◆ SCB_CFSR_STKERR_Msk [9/11]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

◆ SCB_CFSR_STKERR_Msk [10/11]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

◆ SCB_CFSR_STKERR_Msk [11/11]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

◆ SCB_CFSR_STKERR_Pos [1/11]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

◆ SCB_CFSR_STKERR_Pos [2/11]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

◆ SCB_CFSR_STKERR_Pos [3/11]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

◆ SCB_CFSR_STKERR_Pos [4/11]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

◆ SCB_CFSR_STKERR_Pos [5/11]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

◆ SCB_CFSR_STKERR_Pos [6/11]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

◆ SCB_CFSR_STKERR_Pos [7/11]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

◆ SCB_CFSR_STKERR_Pos [8/11]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

◆ SCB_CFSR_STKERR_Pos [9/11]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

◆ SCB_CFSR_STKERR_Pos [10/11]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

◆ SCB_CFSR_STKERR_Pos [11/11]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

◆ SCB_CFSR_STKOF_Msk [1/7]

#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)

SCB CFSR (UFSR): STKOF Mask

◆ SCB_CFSR_STKOF_Msk [2/7]

#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)

SCB CFSR (UFSR): STKOF Mask

◆ SCB_CFSR_STKOF_Msk [3/7]

#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)

SCB CFSR (UFSR): STKOF Mask

◆ SCB_CFSR_STKOF_Msk [4/7]

#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)

SCB CFSR (UFSR): STKOF Mask

◆ SCB_CFSR_STKOF_Msk [5/7]

#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)

SCB CFSR (UFSR): STKOF Mask

◆ SCB_CFSR_STKOF_Msk [6/7]

#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)

SCB CFSR (UFSR): STKOF Mask

◆ SCB_CFSR_STKOF_Msk [7/7]

#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)

SCB CFSR (UFSR): STKOF Mask

◆ SCB_CFSR_STKOF_Pos [1/7]

#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)

SCB CFSR (UFSR): STKOF Position

◆ SCB_CFSR_STKOF_Pos [2/7]

#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)

SCB CFSR (UFSR): STKOF Position

◆ SCB_CFSR_STKOF_Pos [3/7]

#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)

SCB CFSR (UFSR): STKOF Position

◆ SCB_CFSR_STKOF_Pos [4/7]

#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)

SCB CFSR (UFSR): STKOF Position

◆ SCB_CFSR_STKOF_Pos [5/7]

#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)

SCB CFSR (UFSR): STKOF Position

◆ SCB_CFSR_STKOF_Pos [6/7]

#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)

SCB CFSR (UFSR): STKOF Position

◆ SCB_CFSR_STKOF_Pos [7/7]

#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)

SCB CFSR (UFSR): STKOF Position

◆ SCB_CFSR_UNALIGNED_Msk [1/11]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

◆ SCB_CFSR_UNALIGNED_Msk [2/11]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

◆ SCB_CFSR_UNALIGNED_Msk [3/11]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

◆ SCB_CFSR_UNALIGNED_Msk [4/11]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

◆ SCB_CFSR_UNALIGNED_Msk [5/11]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

◆ SCB_CFSR_UNALIGNED_Msk [6/11]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

◆ SCB_CFSR_UNALIGNED_Msk [7/11]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

◆ SCB_CFSR_UNALIGNED_Msk [8/11]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

◆ SCB_CFSR_UNALIGNED_Msk [9/11]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

◆ SCB_CFSR_UNALIGNED_Msk [10/11]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

◆ SCB_CFSR_UNALIGNED_Msk [11/11]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

◆ SCB_CFSR_UNALIGNED_Pos [1/11]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

◆ SCB_CFSR_UNALIGNED_Pos [2/11]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

◆ SCB_CFSR_UNALIGNED_Pos [3/11]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

◆ SCB_CFSR_UNALIGNED_Pos [4/11]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

◆ SCB_CFSR_UNALIGNED_Pos [5/11]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

◆ SCB_CFSR_UNALIGNED_Pos [6/11]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

◆ SCB_CFSR_UNALIGNED_Pos [7/11]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

◆ SCB_CFSR_UNALIGNED_Pos [8/11]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

◆ SCB_CFSR_UNALIGNED_Pos [9/11]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

◆ SCB_CFSR_UNALIGNED_Pos [10/11]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

◆ SCB_CFSR_UNALIGNED_Pos [11/11]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

◆ SCB_CFSR_UNDEFINSTR_Msk [1/11]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

◆ SCB_CFSR_UNDEFINSTR_Msk [2/11]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

◆ SCB_CFSR_UNDEFINSTR_Msk [3/11]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

◆ SCB_CFSR_UNDEFINSTR_Msk [4/11]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

◆ SCB_CFSR_UNDEFINSTR_Msk [5/11]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

◆ SCB_CFSR_UNDEFINSTR_Msk [6/11]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

◆ SCB_CFSR_UNDEFINSTR_Msk [7/11]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

◆ SCB_CFSR_UNDEFINSTR_Msk [8/11]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

◆ SCB_CFSR_UNDEFINSTR_Msk [9/11]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

◆ SCB_CFSR_UNDEFINSTR_Msk [10/11]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

◆ SCB_CFSR_UNDEFINSTR_Msk [11/11]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

◆ SCB_CFSR_UNDEFINSTR_Pos [1/11]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

◆ SCB_CFSR_UNDEFINSTR_Pos [2/11]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

◆ SCB_CFSR_UNDEFINSTR_Pos [3/11]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

◆ SCB_CFSR_UNDEFINSTR_Pos [4/11]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

◆ SCB_CFSR_UNDEFINSTR_Pos [5/11]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

◆ SCB_CFSR_UNDEFINSTR_Pos [6/11]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

◆ SCB_CFSR_UNDEFINSTR_Pos [7/11]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

◆ SCB_CFSR_UNDEFINSTR_Pos [8/11]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

◆ SCB_CFSR_UNDEFINSTR_Pos [9/11]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

◆ SCB_CFSR_UNDEFINSTR_Pos [10/11]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

◆ SCB_CFSR_UNDEFINSTR_Pos [11/11]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

◆ SCB_CFSR_UNSTKERR_Msk [1/11]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

◆ SCB_CFSR_UNSTKERR_Msk [2/11]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

◆ SCB_CFSR_UNSTKERR_Msk [3/11]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

◆ SCB_CFSR_UNSTKERR_Msk [4/11]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

◆ SCB_CFSR_UNSTKERR_Msk [5/11]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

◆ SCB_CFSR_UNSTKERR_Msk [6/11]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

◆ SCB_CFSR_UNSTKERR_Msk [7/11]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

◆ SCB_CFSR_UNSTKERR_Msk [8/11]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

◆ SCB_CFSR_UNSTKERR_Msk [9/11]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

◆ SCB_CFSR_UNSTKERR_Msk [10/11]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

◆ SCB_CFSR_UNSTKERR_Msk [11/11]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

◆ SCB_CFSR_UNSTKERR_Pos [1/11]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

◆ SCB_CFSR_UNSTKERR_Pos [2/11]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

◆ SCB_CFSR_UNSTKERR_Pos [3/11]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

◆ SCB_CFSR_UNSTKERR_Pos [4/11]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

◆ SCB_CFSR_UNSTKERR_Pos [5/11]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

◆ SCB_CFSR_UNSTKERR_Pos [6/11]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

◆ SCB_CFSR_UNSTKERR_Pos [7/11]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

◆ SCB_CFSR_UNSTKERR_Pos [8/11]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

◆ SCB_CFSR_UNSTKERR_Pos [9/11]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

◆ SCB_CFSR_UNSTKERR_Pos [10/11]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

◆ SCB_CFSR_UNSTKERR_Pos [11/11]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

◆ SCB_CFSR_USGFAULTSR_Msk [1/11]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

◆ SCB_CFSR_USGFAULTSR_Msk [2/11]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

◆ SCB_CFSR_USGFAULTSR_Msk [3/11]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

◆ SCB_CFSR_USGFAULTSR_Msk [4/11]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

◆ SCB_CFSR_USGFAULTSR_Msk [5/11]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

◆ SCB_CFSR_USGFAULTSR_Msk [6/11]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

◆ SCB_CFSR_USGFAULTSR_Msk [7/11]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

◆ SCB_CFSR_USGFAULTSR_Msk [8/11]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

◆ SCB_CFSR_USGFAULTSR_Msk [9/11]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

◆ SCB_CFSR_USGFAULTSR_Msk [10/11]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

◆ SCB_CFSR_USGFAULTSR_Msk [11/11]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

◆ SCB_CFSR_USGFAULTSR_Pos [1/11]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

◆ SCB_CFSR_USGFAULTSR_Pos [2/11]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

◆ SCB_CFSR_USGFAULTSR_Pos [3/11]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

◆ SCB_CFSR_USGFAULTSR_Pos [4/11]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

◆ SCB_CFSR_USGFAULTSR_Pos [5/11]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

◆ SCB_CFSR_USGFAULTSR_Pos [6/11]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

◆ SCB_CFSR_USGFAULTSR_Pos [7/11]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

◆ SCB_CFSR_USGFAULTSR_Pos [8/11]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

◆ SCB_CFSR_USGFAULTSR_Pos [9/11]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

◆ SCB_CFSR_USGFAULTSR_Pos [10/11]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

◆ SCB_CFSR_USGFAULTSR_Pos [11/11]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

◆ SCB_CLIDR_DC_Msk

#define SCB_CLIDR_DC_Msk   (1UL << SCB_CLIDR_DC_Pos)

SCB CLIDR: DC Mask

◆ SCB_CLIDR_DC_Pos

#define SCB_CLIDR_DC_Pos   1U

SCB CLIDR: DC Position

◆ SCB_CLIDR_IC_Msk

#define SCB_CLIDR_IC_Msk   (1UL << SCB_CLIDR_IC_Pos)

SCB CLIDR: IC Mask

◆ SCB_CLIDR_IC_Pos

#define SCB_CLIDR_IC_Pos   0U

SCB CLIDR: IC Position

◆ SCB_CLIDR_LOC_Msk [1/8]

#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

◆ SCB_CLIDR_LOC_Msk [2/8]

#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

◆ SCB_CLIDR_LOC_Msk [3/8]

#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

◆ SCB_CLIDR_LOC_Msk [4/8]

#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

◆ SCB_CLIDR_LOC_Msk [5/8]

#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

◆ SCB_CLIDR_LOC_Msk [6/8]

#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

◆ SCB_CLIDR_LOC_Msk [7/8]

#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

◆ SCB_CLIDR_LOC_Msk [8/8]

#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

◆ SCB_CLIDR_LOC_Pos [1/8]

#define SCB_CLIDR_LOC_Pos   24U

SCB CLIDR: LoC Position

◆ SCB_CLIDR_LOC_Pos [2/8]

#define SCB_CLIDR_LOC_Pos   24U

SCB CLIDR: LoC Position

◆ SCB_CLIDR_LOC_Pos [3/8]

#define SCB_CLIDR_LOC_Pos   24U

SCB CLIDR: LoC Position

◆ SCB_CLIDR_LOC_Pos [4/8]

#define SCB_CLIDR_LOC_Pos   24U

SCB CLIDR: LoC Position

◆ SCB_CLIDR_LOC_Pos [5/8]

#define SCB_CLIDR_LOC_Pos   24U

SCB CLIDR: LoC Position

◆ SCB_CLIDR_LOC_Pos [6/8]

#define SCB_CLIDR_LOC_Pos   24U

SCB CLIDR: LoC Position

◆ SCB_CLIDR_LOC_Pos [7/8]

#define SCB_CLIDR_LOC_Pos   24U

SCB CLIDR: LoC Position

◆ SCB_CLIDR_LOC_Pos [8/8]

#define SCB_CLIDR_LOC_Pos   24U

SCB CLIDR: LoC Position

◆ SCB_CLIDR_LOUU_Msk [1/8]

#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

◆ SCB_CLIDR_LOUU_Msk [2/8]

#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

◆ SCB_CLIDR_LOUU_Msk [3/8]

#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

◆ SCB_CLIDR_LOUU_Msk [4/8]

#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

◆ SCB_CLIDR_LOUU_Msk [5/8]

#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

◆ SCB_CLIDR_LOUU_Msk [6/8]

#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

◆ SCB_CLIDR_LOUU_Msk [7/8]

#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

◆ SCB_CLIDR_LOUU_Msk [8/8]

#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

◆ SCB_CLIDR_LOUU_Pos [1/8]

#define SCB_CLIDR_LOUU_Pos   27U

SCB CLIDR: LoUU Position

◆ SCB_CLIDR_LOUU_Pos [2/8]

#define SCB_CLIDR_LOUU_Pos   27U

SCB CLIDR: LoUU Position

◆ SCB_CLIDR_LOUU_Pos [3/8]

#define SCB_CLIDR_LOUU_Pos   27U

SCB CLIDR: LoUU Position

◆ SCB_CLIDR_LOUU_Pos [4/8]

#define SCB_CLIDR_LOUU_Pos   27U

SCB CLIDR: LoUU Position

◆ SCB_CLIDR_LOUU_Pos [5/8]

#define SCB_CLIDR_LOUU_Pos   27U

SCB CLIDR: LoUU Position

◆ SCB_CLIDR_LOUU_Pos [6/8]

#define SCB_CLIDR_LOUU_Pos   27U

SCB CLIDR: LoUU Position

◆ SCB_CLIDR_LOUU_Pos [7/8]

#define SCB_CLIDR_LOUU_Pos   27U

SCB CLIDR: LoUU Position

◆ SCB_CLIDR_LOUU_Pos [8/8]

#define SCB_CLIDR_LOUU_Pos   27U

SCB CLIDR: LoUU Position

◆ SCB_CPUID_ARCHITECTURE_Msk [1/17]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

◆ SCB_CPUID_ARCHITECTURE_Msk [2/17]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

◆ SCB_CPUID_ARCHITECTURE_Msk [3/17]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

◆ SCB_CPUID_ARCHITECTURE_Msk [4/17]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

◆ SCB_CPUID_ARCHITECTURE_Msk [5/17]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

◆ SCB_CPUID_ARCHITECTURE_Msk [6/17]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

◆ SCB_CPUID_ARCHITECTURE_Msk [7/17]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

◆ SCB_CPUID_ARCHITECTURE_Msk [8/17]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

◆ SCB_CPUID_ARCHITECTURE_Msk [9/17]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

◆ SCB_CPUID_ARCHITECTURE_Msk [10/17]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

◆ SCB_CPUID_ARCHITECTURE_Msk [11/17]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

◆ SCB_CPUID_ARCHITECTURE_Msk [12/17]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

◆ SCB_CPUID_ARCHITECTURE_Msk [13/17]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

◆ SCB_CPUID_ARCHITECTURE_Msk [14/17]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

◆ SCB_CPUID_ARCHITECTURE_Msk [15/17]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

◆ SCB_CPUID_ARCHITECTURE_Msk [16/17]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

◆ SCB_CPUID_ARCHITECTURE_Msk [17/17]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

◆ SCB_CPUID_ARCHITECTURE_Pos [1/17]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

◆ SCB_CPUID_ARCHITECTURE_Pos [2/17]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

◆ SCB_CPUID_ARCHITECTURE_Pos [3/17]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

◆ SCB_CPUID_ARCHITECTURE_Pos [4/17]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

◆ SCB_CPUID_ARCHITECTURE_Pos [5/17]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

◆ SCB_CPUID_ARCHITECTURE_Pos [6/17]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

◆ SCB_CPUID_ARCHITECTURE_Pos [7/17]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

◆ SCB_CPUID_ARCHITECTURE_Pos [8/17]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

◆ SCB_CPUID_ARCHITECTURE_Pos [9/17]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

◆ SCB_CPUID_ARCHITECTURE_Pos [10/17]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

◆ SCB_CPUID_ARCHITECTURE_Pos [11/17]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

◆ SCB_CPUID_ARCHITECTURE_Pos [12/17]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

◆ SCB_CPUID_ARCHITECTURE_Pos [13/17]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

◆ SCB_CPUID_ARCHITECTURE_Pos [14/17]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

◆ SCB_CPUID_ARCHITECTURE_Pos [15/17]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

◆ SCB_CPUID_ARCHITECTURE_Pos [16/17]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

◆ SCB_CPUID_ARCHITECTURE_Pos [17/17]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

◆ SCB_CPUID_IMPLEMENTER_Msk [1/17]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

◆ SCB_CPUID_IMPLEMENTER_Msk [2/17]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

◆ SCB_CPUID_IMPLEMENTER_Msk [3/17]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

◆ SCB_CPUID_IMPLEMENTER_Msk [4/17]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

◆ SCB_CPUID_IMPLEMENTER_Msk [5/17]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

◆ SCB_CPUID_IMPLEMENTER_Msk [6/17]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

◆ SCB_CPUID_IMPLEMENTER_Msk [7/17]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

◆ SCB_CPUID_IMPLEMENTER_Msk [8/17]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

◆ SCB_CPUID_IMPLEMENTER_Msk [9/17]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

◆ SCB_CPUID_IMPLEMENTER_Msk [10/17]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

◆ SCB_CPUID_IMPLEMENTER_Msk [11/17]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

◆ SCB_CPUID_IMPLEMENTER_Msk [12/17]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

◆ SCB_CPUID_IMPLEMENTER_Msk [13/17]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

◆ SCB_CPUID_IMPLEMENTER_Msk [14/17]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

◆ SCB_CPUID_IMPLEMENTER_Msk [15/17]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

◆ SCB_CPUID_IMPLEMENTER_Msk [16/17]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

◆ SCB_CPUID_IMPLEMENTER_Msk [17/17]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

◆ SCB_CPUID_IMPLEMENTER_Pos [1/17]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

◆ SCB_CPUID_IMPLEMENTER_Pos [2/17]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

◆ SCB_CPUID_IMPLEMENTER_Pos [3/17]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

◆ SCB_CPUID_IMPLEMENTER_Pos [4/17]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

◆ SCB_CPUID_IMPLEMENTER_Pos [5/17]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

◆ SCB_CPUID_IMPLEMENTER_Pos [6/17]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

◆ SCB_CPUID_IMPLEMENTER_Pos [7/17]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

◆ SCB_CPUID_IMPLEMENTER_Pos [8/17]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

◆ SCB_CPUID_IMPLEMENTER_Pos [9/17]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

◆ SCB_CPUID_IMPLEMENTER_Pos [10/17]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

◆ SCB_CPUID_IMPLEMENTER_Pos [11/17]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

◆ SCB_CPUID_IMPLEMENTER_Pos [12/17]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

◆ SCB_CPUID_IMPLEMENTER_Pos [13/17]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

◆ SCB_CPUID_IMPLEMENTER_Pos [14/17]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

◆ SCB_CPUID_IMPLEMENTER_Pos [15/17]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

◆ SCB_CPUID_IMPLEMENTER_Pos [16/17]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

◆ SCB_CPUID_IMPLEMENTER_Pos [17/17]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

◆ SCB_CPUID_PARTNO_Msk [1/17]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

◆ SCB_CPUID_PARTNO_Msk [2/17]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

◆ SCB_CPUID_PARTNO_Msk [3/17]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

◆ SCB_CPUID_PARTNO_Msk [4/17]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

◆ SCB_CPUID_PARTNO_Msk [5/17]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

◆ SCB_CPUID_PARTNO_Msk [6/17]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

◆ SCB_CPUID_PARTNO_Msk [7/17]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

◆ SCB_CPUID_PARTNO_Msk [8/17]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

◆ SCB_CPUID_PARTNO_Msk [9/17]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

◆ SCB_CPUID_PARTNO_Msk [10/17]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

◆ SCB_CPUID_PARTNO_Msk [11/17]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

◆ SCB_CPUID_PARTNO_Msk [12/17]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

◆ SCB_CPUID_PARTNO_Msk [13/17]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

◆ SCB_CPUID_PARTNO_Msk [14/17]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

◆ SCB_CPUID_PARTNO_Msk [15/17]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

◆ SCB_CPUID_PARTNO_Msk [16/17]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

◆ SCB_CPUID_PARTNO_Msk [17/17]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

◆ SCB_CPUID_PARTNO_Pos [1/17]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

◆ SCB_CPUID_PARTNO_Pos [2/17]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

◆ SCB_CPUID_PARTNO_Pos [3/17]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

◆ SCB_CPUID_PARTNO_Pos [4/17]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

◆ SCB_CPUID_PARTNO_Pos [5/17]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

◆ SCB_CPUID_PARTNO_Pos [6/17]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

◆ SCB_CPUID_PARTNO_Pos [7/17]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

◆ SCB_CPUID_PARTNO_Pos [8/17]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

◆ SCB_CPUID_PARTNO_Pos [9/17]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

◆ SCB_CPUID_PARTNO_Pos [10/17]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

◆ SCB_CPUID_PARTNO_Pos [11/17]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

◆ SCB_CPUID_PARTNO_Pos [12/17]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

◆ SCB_CPUID_PARTNO_Pos [13/17]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

◆ SCB_CPUID_PARTNO_Pos [14/17]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

◆ SCB_CPUID_PARTNO_Pos [15/17]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

◆ SCB_CPUID_PARTNO_Pos [16/17]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

◆ SCB_CPUID_PARTNO_Pos [17/17]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

◆ SCB_CPUID_REVISION_Msk [1/17]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

◆ SCB_CPUID_REVISION_Msk [2/17]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

◆ SCB_CPUID_REVISION_Msk [3/17]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

◆ SCB_CPUID_REVISION_Msk [4/17]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

◆ SCB_CPUID_REVISION_Msk [5/17]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

◆ SCB_CPUID_REVISION_Msk [6/17]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

◆ SCB_CPUID_REVISION_Msk [7/17]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

◆ SCB_CPUID_REVISION_Msk [8/17]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

◆ SCB_CPUID_REVISION_Msk [9/17]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

◆ SCB_CPUID_REVISION_Msk [10/17]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

◆ SCB_CPUID_REVISION_Msk [11/17]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

◆ SCB_CPUID_REVISION_Msk [12/17]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

◆ SCB_CPUID_REVISION_Msk [13/17]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

◆ SCB_CPUID_REVISION_Msk [14/17]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

◆ SCB_CPUID_REVISION_Msk [15/17]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

◆ SCB_CPUID_REVISION_Msk [16/17]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

◆ SCB_CPUID_REVISION_Msk [17/17]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

◆ SCB_CPUID_REVISION_Pos [1/17]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

◆ SCB_CPUID_REVISION_Pos [2/17]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

◆ SCB_CPUID_REVISION_Pos [3/17]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

◆ SCB_CPUID_REVISION_Pos [4/17]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

◆ SCB_CPUID_REVISION_Pos [5/17]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

◆ SCB_CPUID_REVISION_Pos [6/17]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

◆ SCB_CPUID_REVISION_Pos [7/17]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

◆ SCB_CPUID_REVISION_Pos [8/17]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

◆ SCB_CPUID_REVISION_Pos [9/17]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

◆ SCB_CPUID_REVISION_Pos [10/17]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

◆ SCB_CPUID_REVISION_Pos [11/17]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

◆ SCB_CPUID_REVISION_Pos [12/17]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

◆ SCB_CPUID_REVISION_Pos [13/17]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

◆ SCB_CPUID_REVISION_Pos [14/17]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

◆ SCB_CPUID_REVISION_Pos [15/17]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

◆ SCB_CPUID_REVISION_Pos [16/17]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

◆ SCB_CPUID_REVISION_Pos [17/17]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

◆ SCB_CPUID_VARIANT_Msk [1/17]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

◆ SCB_CPUID_VARIANT_Msk [2/17]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

◆ SCB_CPUID_VARIANT_Msk [3/17]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

◆ SCB_CPUID_VARIANT_Msk [4/17]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

◆ SCB_CPUID_VARIANT_Msk [5/17]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

◆ SCB_CPUID_VARIANT_Msk [6/17]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

◆ SCB_CPUID_VARIANT_Msk [7/17]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

◆ SCB_CPUID_VARIANT_Msk [8/17]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

◆ SCB_CPUID_VARIANT_Msk [9/17]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

◆ SCB_CPUID_VARIANT_Msk [10/17]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

◆ SCB_CPUID_VARIANT_Msk [11/17]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

◆ SCB_CPUID_VARIANT_Msk [12/17]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

◆ SCB_CPUID_VARIANT_Msk [13/17]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

◆ SCB_CPUID_VARIANT_Msk [14/17]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

◆ SCB_CPUID_VARIANT_Msk [15/17]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

◆ SCB_CPUID_VARIANT_Msk [16/17]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

◆ SCB_CPUID_VARIANT_Msk [17/17]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

◆ SCB_CPUID_VARIANT_Pos [1/17]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

◆ SCB_CPUID_VARIANT_Pos [2/17]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

◆ SCB_CPUID_VARIANT_Pos [3/17]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

◆ SCB_CPUID_VARIANT_Pos [4/17]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

◆ SCB_CPUID_VARIANT_Pos [5/17]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

◆ SCB_CPUID_VARIANT_Pos [6/17]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

◆ SCB_CPUID_VARIANT_Pos [7/17]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

◆ SCB_CPUID_VARIANT_Pos [8/17]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

◆ SCB_CPUID_VARIANT_Pos [9/17]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

◆ SCB_CPUID_VARIANT_Pos [10/17]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

◆ SCB_CPUID_VARIANT_Pos [11/17]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

◆ SCB_CPUID_VARIANT_Pos [12/17]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

◆ SCB_CPUID_VARIANT_Pos [13/17]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

◆ SCB_CPUID_VARIANT_Pos [14/17]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

◆ SCB_CPUID_VARIANT_Pos [15/17]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

◆ SCB_CPUID_VARIANT_Pos [16/17]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

◆ SCB_CPUID_VARIANT_Pos [17/17]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

◆ SCB_CSSELR_IND_Msk [1/8]

#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

◆ SCB_CSSELR_IND_Msk [2/8]

#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

◆ SCB_CSSELR_IND_Msk [3/8]

#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

◆ SCB_CSSELR_IND_Msk [4/8]

#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

◆ SCB_CSSELR_IND_Msk [5/8]

#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

◆ SCB_CSSELR_IND_Msk [6/8]

#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

◆ SCB_CSSELR_IND_Msk [7/8]

#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

◆ SCB_CSSELR_IND_Msk [8/8]

#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

◆ SCB_CSSELR_IND_Pos [1/8]

#define SCB_CSSELR_IND_Pos   0U

SCB CSSELR: InD Position

◆ SCB_CSSELR_IND_Pos [2/8]

#define SCB_CSSELR_IND_Pos   0U

SCB CSSELR: InD Position

◆ SCB_CSSELR_IND_Pos [3/8]

#define SCB_CSSELR_IND_Pos   0U

SCB CSSELR: InD Position

◆ SCB_CSSELR_IND_Pos [4/8]

#define SCB_CSSELR_IND_Pos   0U

SCB CSSELR: InD Position

◆ SCB_CSSELR_IND_Pos [5/8]

#define SCB_CSSELR_IND_Pos   0U

SCB CSSELR: InD Position

◆ SCB_CSSELR_IND_Pos [6/8]

#define SCB_CSSELR_IND_Pos   0U

SCB CSSELR: InD Position

◆ SCB_CSSELR_IND_Pos [7/8]

#define SCB_CSSELR_IND_Pos   0U

SCB CSSELR: InD Position

◆ SCB_CSSELR_IND_Pos [8/8]

#define SCB_CSSELR_IND_Pos   0U

SCB CSSELR: InD Position

◆ SCB_CSSELR_LEVEL_Msk [1/8]

#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

◆ SCB_CSSELR_LEVEL_Msk [2/8]

#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

◆ SCB_CSSELR_LEVEL_Msk [3/8]

#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

◆ SCB_CSSELR_LEVEL_Msk [4/8]

#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

◆ SCB_CSSELR_LEVEL_Msk [5/8]

#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

◆ SCB_CSSELR_LEVEL_Msk [6/8]

#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

◆ SCB_CSSELR_LEVEL_Msk [7/8]

#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

◆ SCB_CSSELR_LEVEL_Msk [8/8]

#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

◆ SCB_CSSELR_LEVEL_Pos [1/8]

#define SCB_CSSELR_LEVEL_Pos   1U

SCB CSSELR: Level Position

◆ SCB_CSSELR_LEVEL_Pos [2/8]

#define SCB_CSSELR_LEVEL_Pos   1U

SCB CSSELR: Level Position

◆ SCB_CSSELR_LEVEL_Pos [3/8]

#define SCB_CSSELR_LEVEL_Pos   1U

SCB CSSELR: Level Position

◆ SCB_CSSELR_LEVEL_Pos [4/8]

#define SCB_CSSELR_LEVEL_Pos   1U

SCB CSSELR: Level Position

◆ SCB_CSSELR_LEVEL_Pos [5/8]

#define SCB_CSSELR_LEVEL_Pos   1U

SCB CSSELR: Level Position

◆ SCB_CSSELR_LEVEL_Pos [6/8]

#define SCB_CSSELR_LEVEL_Pos   1U

SCB CSSELR: Level Position

◆ SCB_CSSELR_LEVEL_Pos [7/8]

#define SCB_CSSELR_LEVEL_Pos   1U

SCB CSSELR: Level Position

◆ SCB_CSSELR_LEVEL_Pos [8/8]

#define SCB_CSSELR_LEVEL_Pos   1U

SCB CSSELR: Level Position

◆ SCB_CTR_CWG_Msk [1/8]

#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

◆ SCB_CTR_CWG_Msk [2/8]

#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

◆ SCB_CTR_CWG_Msk [3/8]

#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

◆ SCB_CTR_CWG_Msk [4/8]

#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

◆ SCB_CTR_CWG_Msk [5/8]

#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

◆ SCB_CTR_CWG_Msk [6/8]

#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

◆ SCB_CTR_CWG_Msk [7/8]

#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

◆ SCB_CTR_CWG_Msk [8/8]

#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

◆ SCB_CTR_CWG_Pos [1/8]

#define SCB_CTR_CWG_Pos   24U

SCB CTR: CWG Position

◆ SCB_CTR_CWG_Pos [2/8]

#define SCB_CTR_CWG_Pos   24U

SCB CTR: CWG Position

◆ SCB_CTR_CWG_Pos [3/8]

#define SCB_CTR_CWG_Pos   24U

SCB CTR: CWG Position

◆ SCB_CTR_CWG_Pos [4/8]

#define SCB_CTR_CWG_Pos   24U

SCB CTR: CWG Position

◆ SCB_CTR_CWG_Pos [5/8]

#define SCB_CTR_CWG_Pos   24U

SCB CTR: CWG Position

◆ SCB_CTR_CWG_Pos [6/8]

#define SCB_CTR_CWG_Pos   24U

SCB CTR: CWG Position

◆ SCB_CTR_CWG_Pos [7/8]

#define SCB_CTR_CWG_Pos   24U

SCB CTR: CWG Position

◆ SCB_CTR_CWG_Pos [8/8]

#define SCB_CTR_CWG_Pos   24U

SCB CTR: CWG Position

◆ SCB_CTR_DMINLINE_Msk [1/8]

#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

◆ SCB_CTR_DMINLINE_Msk [2/8]

#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

◆ SCB_CTR_DMINLINE_Msk [3/8]

#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

◆ SCB_CTR_DMINLINE_Msk [4/8]

#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

◆ SCB_CTR_DMINLINE_Msk [5/8]

#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

◆ SCB_CTR_DMINLINE_Msk [6/8]

#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

◆ SCB_CTR_DMINLINE_Msk [7/8]

#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

◆ SCB_CTR_DMINLINE_Msk [8/8]

#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

◆ SCB_CTR_DMINLINE_Pos [1/8]

#define SCB_CTR_DMINLINE_Pos   16U

SCB CTR: DminLine Position

◆ SCB_CTR_DMINLINE_Pos [2/8]

#define SCB_CTR_DMINLINE_Pos   16U

SCB CTR: DminLine Position

◆ SCB_CTR_DMINLINE_Pos [3/8]

#define SCB_CTR_DMINLINE_Pos   16U

SCB CTR: DminLine Position

◆ SCB_CTR_DMINLINE_Pos [4/8]

#define SCB_CTR_DMINLINE_Pos   16U

SCB CTR: DminLine Position

◆ SCB_CTR_DMINLINE_Pos [5/8]

#define SCB_CTR_DMINLINE_Pos   16U

SCB CTR: DminLine Position

◆ SCB_CTR_DMINLINE_Pos [6/8]

#define SCB_CTR_DMINLINE_Pos   16U

SCB CTR: DminLine Position

◆ SCB_CTR_DMINLINE_Pos [7/8]

#define SCB_CTR_DMINLINE_Pos   16U

SCB CTR: DminLine Position

◆ SCB_CTR_DMINLINE_Pos [8/8]

#define SCB_CTR_DMINLINE_Pos   16U

SCB CTR: DminLine Position

◆ SCB_CTR_ERG_Msk [1/8]

#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

◆ SCB_CTR_ERG_Msk [2/8]

#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

◆ SCB_CTR_ERG_Msk [3/8]

#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

◆ SCB_CTR_ERG_Msk [4/8]

#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

◆ SCB_CTR_ERG_Msk [5/8]

#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

◆ SCB_CTR_ERG_Msk [6/8]

#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

◆ SCB_CTR_ERG_Msk [7/8]

#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

◆ SCB_CTR_ERG_Msk [8/8]

#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

◆ SCB_CTR_ERG_Pos [1/8]

#define SCB_CTR_ERG_Pos   20U

SCB CTR: ERG Position

◆ SCB_CTR_ERG_Pos [2/8]

#define SCB_CTR_ERG_Pos   20U

SCB CTR: ERG Position

◆ SCB_CTR_ERG_Pos [3/8]

#define SCB_CTR_ERG_Pos   20U

SCB CTR: ERG Position

◆ SCB_CTR_ERG_Pos [4/8]

#define SCB_CTR_ERG_Pos   20U

SCB CTR: ERG Position

◆ SCB_CTR_ERG_Pos [5/8]

#define SCB_CTR_ERG_Pos   20U

SCB CTR: ERG Position

◆ SCB_CTR_ERG_Pos [6/8]

#define SCB_CTR_ERG_Pos   20U

SCB CTR: ERG Position

◆ SCB_CTR_ERG_Pos [7/8]

#define SCB_CTR_ERG_Pos   20U

SCB CTR: ERG Position

◆ SCB_CTR_ERG_Pos [8/8]

#define SCB_CTR_ERG_Pos   20U

SCB CTR: ERG Position

◆ SCB_CTR_FORMAT_Msk [1/8]

#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

◆ SCB_CTR_FORMAT_Msk [2/8]

#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

◆ SCB_CTR_FORMAT_Msk [3/8]

#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

◆ SCB_CTR_FORMAT_Msk [4/8]

#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

◆ SCB_CTR_FORMAT_Msk [5/8]

#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

◆ SCB_CTR_FORMAT_Msk [6/8]

#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

◆ SCB_CTR_FORMAT_Msk [7/8]

#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

◆ SCB_CTR_FORMAT_Msk [8/8]

#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

◆ SCB_CTR_FORMAT_Pos [1/8]

#define SCB_CTR_FORMAT_Pos   29U

SCB CTR: Format Position

◆ SCB_CTR_FORMAT_Pos [2/8]

#define SCB_CTR_FORMAT_Pos   29U

SCB CTR: Format Position

◆ SCB_CTR_FORMAT_Pos [3/8]

#define SCB_CTR_FORMAT_Pos   29U

SCB CTR: Format Position

◆ SCB_CTR_FORMAT_Pos [4/8]

#define SCB_CTR_FORMAT_Pos   29U

SCB CTR: Format Position

◆ SCB_CTR_FORMAT_Pos [5/8]

#define SCB_CTR_FORMAT_Pos   29U

SCB CTR: Format Position

◆ SCB_CTR_FORMAT_Pos [6/8]

#define SCB_CTR_FORMAT_Pos   29U

SCB CTR: Format Position

◆ SCB_CTR_FORMAT_Pos [7/8]

#define SCB_CTR_FORMAT_Pos   29U

SCB CTR: Format Position

◆ SCB_CTR_FORMAT_Pos [8/8]

#define SCB_CTR_FORMAT_Pos   29U

SCB CTR: Format Position

◆ SCB_CTR_IMINLINE_Msk [1/8]

#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

◆ SCB_CTR_IMINLINE_Msk [2/8]

#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

◆ SCB_CTR_IMINLINE_Msk [3/8]

#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

◆ SCB_CTR_IMINLINE_Msk [4/8]

#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

◆ SCB_CTR_IMINLINE_Msk [5/8]

#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

◆ SCB_CTR_IMINLINE_Msk [6/8]

#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

◆ SCB_CTR_IMINLINE_Msk [7/8]

#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

◆ SCB_CTR_IMINLINE_Msk [8/8]

#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

◆ SCB_CTR_IMINLINE_Pos [1/8]

#define SCB_CTR_IMINLINE_Pos   0U

SCB CTR: ImInLine Position

◆ SCB_CTR_IMINLINE_Pos [2/8]

#define SCB_CTR_IMINLINE_Pos   0U

SCB CTR: ImInLine Position

◆ SCB_CTR_IMINLINE_Pos [3/8]

#define SCB_CTR_IMINLINE_Pos   0U

SCB CTR: ImInLine Position

◆ SCB_CTR_IMINLINE_Pos [4/8]

#define SCB_CTR_IMINLINE_Pos   0U

SCB CTR: ImInLine Position

◆ SCB_CTR_IMINLINE_Pos [5/8]

#define SCB_CTR_IMINLINE_Pos   0U

SCB CTR: ImInLine Position

◆ SCB_CTR_IMINLINE_Pos [6/8]

#define SCB_CTR_IMINLINE_Pos   0U

SCB CTR: ImInLine Position

◆ SCB_CTR_IMINLINE_Pos [7/8]

#define SCB_CTR_IMINLINE_Pos   0U

SCB CTR: ImInLine Position

◆ SCB_CTR_IMINLINE_Pos [8/8]

#define SCB_CTR_IMINLINE_Pos   0U

SCB CTR: ImInLine Position

◆ SCB_DCCISW_LEVEL_Msk

#define SCB_DCCISW_LEVEL_Msk   (7UL << SCB_DCCISW_LEVEL_Pos)

SCB DCCISW: Level Mask

◆ SCB_DCCISW_LEVEL_Pos

#define SCB_DCCISW_LEVEL_Pos   1U

SCB DCCISW: Level Position

◆ SCB_DCCISW_SET_Msk [1/8]

#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

◆ SCB_DCCISW_SET_Msk [2/8]

#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

◆ SCB_DCCISW_SET_Msk [3/8]

#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

◆ SCB_DCCISW_SET_Msk [4/8]

#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

◆ SCB_DCCISW_SET_Msk [5/8]

#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

◆ SCB_DCCISW_SET_Msk [6/8]

#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

◆ SCB_DCCISW_SET_Msk [7/8]

#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

◆ SCB_DCCISW_SET_Msk [8/8]

#define SCB_DCCISW_SET_Msk   (0xFFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

◆ SCB_DCCISW_SET_Pos [1/8]

#define SCB_DCCISW_SET_Pos   5U

SCB DCCISW: Set Position

◆ SCB_DCCISW_SET_Pos [2/8]

#define SCB_DCCISW_SET_Pos   5U

SCB DCCISW: Set Position

◆ SCB_DCCISW_SET_Pos [3/8]

#define SCB_DCCISW_SET_Pos   5U

SCB DCCISW: Set Position

◆ SCB_DCCISW_SET_Pos [4/8]

#define SCB_DCCISW_SET_Pos   5U

SCB DCCISW: Set Position

◆ SCB_DCCISW_SET_Pos [5/8]

#define SCB_DCCISW_SET_Pos   5U

SCB DCCISW: Set Position

◆ SCB_DCCISW_SET_Pos [6/8]

#define SCB_DCCISW_SET_Pos   5U

SCB DCCISW: Set Position

◆ SCB_DCCISW_SET_Pos [7/8]

#define SCB_DCCISW_SET_Pos   5U

SCB DCCISW: Set Position

◆ SCB_DCCISW_SET_Pos [8/8]

#define SCB_DCCISW_SET_Pos   5U

SCB DCCISW: Set Position

◆ SCB_DCCISW_WAY_Msk [1/8]

#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

◆ SCB_DCCISW_WAY_Msk [2/8]

#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

◆ SCB_DCCISW_WAY_Msk [3/8]

#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

◆ SCB_DCCISW_WAY_Msk [4/8]

#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

◆ SCB_DCCISW_WAY_Msk [5/8]

#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

◆ SCB_DCCISW_WAY_Msk [6/8]

#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

◆ SCB_DCCISW_WAY_Msk [7/8]

#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

◆ SCB_DCCISW_WAY_Msk [8/8]

#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

◆ SCB_DCCISW_WAY_Pos [1/8]

#define SCB_DCCISW_WAY_Pos   30U

SCB DCCISW: Way Position

◆ SCB_DCCISW_WAY_Pos [2/8]

#define SCB_DCCISW_WAY_Pos   30U

SCB DCCISW: Way Position

◆ SCB_DCCISW_WAY_Pos [3/8]

#define SCB_DCCISW_WAY_Pos   30U

SCB DCCISW: Way Position

◆ SCB_DCCISW_WAY_Pos [4/8]

#define SCB_DCCISW_WAY_Pos   30U

SCB DCCISW: Way Position

◆ SCB_DCCISW_WAY_Pos [5/8]

#define SCB_DCCISW_WAY_Pos   30U

SCB DCCISW: Way Position

◆ SCB_DCCISW_WAY_Pos [6/8]

#define SCB_DCCISW_WAY_Pos   30U

SCB DCCISW: Way Position

◆ SCB_DCCISW_WAY_Pos [7/8]

#define SCB_DCCISW_WAY_Pos   30U

SCB DCCISW: Way Position

◆ SCB_DCCISW_WAY_Pos [8/8]

#define SCB_DCCISW_WAY_Pos   30U

SCB DCCISW: Way Position

◆ SCB_DCCSW_LEVEL_Msk

#define SCB_DCCSW_LEVEL_Msk   (7UL << SCB_DCCSW_LEVEL_Pos)

SCB DCCSW: Level Mask

◆ SCB_DCCSW_LEVEL_Pos

#define SCB_DCCSW_LEVEL_Pos   1U

SCB DCCSW: Level Position

◆ SCB_DCCSW_SET_Msk [1/8]

#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

◆ SCB_DCCSW_SET_Msk [2/8]

#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

◆ SCB_DCCSW_SET_Msk [3/8]

#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

◆ SCB_DCCSW_SET_Msk [4/8]

#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

◆ SCB_DCCSW_SET_Msk [5/8]

#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

◆ SCB_DCCSW_SET_Msk [6/8]

#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

◆ SCB_DCCSW_SET_Msk [7/8]

#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

◆ SCB_DCCSW_SET_Msk [8/8]

#define SCB_DCCSW_SET_Msk   (0xFFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

◆ SCB_DCCSW_SET_Pos [1/8]

#define SCB_DCCSW_SET_Pos   5U

SCB DCCSW: Set Position

◆ SCB_DCCSW_SET_Pos [2/8]

#define SCB_DCCSW_SET_Pos   5U

SCB DCCSW: Set Position

◆ SCB_DCCSW_SET_Pos [3/8]

#define SCB_DCCSW_SET_Pos   5U

SCB DCCSW: Set Position

◆ SCB_DCCSW_SET_Pos [4/8]

#define SCB_DCCSW_SET_Pos   5U

SCB DCCSW: Set Position

◆ SCB_DCCSW_SET_Pos [5/8]

#define SCB_DCCSW_SET_Pos   5U

SCB DCCSW: Set Position

◆ SCB_DCCSW_SET_Pos [6/8]

#define SCB_DCCSW_SET_Pos   5U

SCB DCCSW: Set Position

◆ SCB_DCCSW_SET_Pos [7/8]

#define SCB_DCCSW_SET_Pos   5U

SCB DCCSW: Set Position

◆ SCB_DCCSW_SET_Pos [8/8]

#define SCB_DCCSW_SET_Pos   5U

SCB DCCSW: Set Position

◆ SCB_DCCSW_WAY_Msk [1/8]

#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

◆ SCB_DCCSW_WAY_Msk [2/8]

#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

◆ SCB_DCCSW_WAY_Msk [3/8]

#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

◆ SCB_DCCSW_WAY_Msk [4/8]

#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

◆ SCB_DCCSW_WAY_Msk [5/8]

#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

◆ SCB_DCCSW_WAY_Msk [6/8]

#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

◆ SCB_DCCSW_WAY_Msk [7/8]

#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

◆ SCB_DCCSW_WAY_Msk [8/8]

#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

◆ SCB_DCCSW_WAY_Pos [1/8]

#define SCB_DCCSW_WAY_Pos   30U

SCB DCCSW: Way Position

◆ SCB_DCCSW_WAY_Pos [2/8]

#define SCB_DCCSW_WAY_Pos   30U

SCB DCCSW: Way Position

◆ SCB_DCCSW_WAY_Pos [3/8]

#define SCB_DCCSW_WAY_Pos   30U

SCB DCCSW: Way Position

◆ SCB_DCCSW_WAY_Pos [4/8]

#define SCB_DCCSW_WAY_Pos   30U

SCB DCCSW: Way Position

◆ SCB_DCCSW_WAY_Pos [5/8]

#define SCB_DCCSW_WAY_Pos   30U

SCB DCCSW: Way Position

◆ SCB_DCCSW_WAY_Pos [6/8]

#define SCB_DCCSW_WAY_Pos   30U

SCB DCCSW: Way Position

◆ SCB_DCCSW_WAY_Pos [7/8]

#define SCB_DCCSW_WAY_Pos   30U

SCB DCCSW: Way Position

◆ SCB_DCCSW_WAY_Pos [8/8]

#define SCB_DCCSW_WAY_Pos   30U

SCB DCCSW: Way Position

◆ SCB_DCISW_LEVEL_Msk

#define SCB_DCISW_LEVEL_Msk   (7UL << SCB_DCISW_LEVEL_Pos)

SCB DCISW: Level Mask

◆ SCB_DCISW_LEVEL_Pos

#define SCB_DCISW_LEVEL_Pos   1U

SCB DCISW: Level Position

◆ SCB_DCISW_SET_Msk [1/8]

#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

◆ SCB_DCISW_SET_Msk [2/8]

#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

◆ SCB_DCISW_SET_Msk [3/8]

#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

◆ SCB_DCISW_SET_Msk [4/8]

#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

◆ SCB_DCISW_SET_Msk [5/8]

#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

◆ SCB_DCISW_SET_Msk [6/8]

#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

◆ SCB_DCISW_SET_Msk [7/8]

#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

◆ SCB_DCISW_SET_Msk [8/8]

#define SCB_DCISW_SET_Msk   (0xFFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

◆ SCB_DCISW_SET_Pos [1/8]

#define SCB_DCISW_SET_Pos   5U

SCB DCISW: Set Position

◆ SCB_DCISW_SET_Pos [2/8]

#define SCB_DCISW_SET_Pos   5U

SCB DCISW: Set Position

◆ SCB_DCISW_SET_Pos [3/8]

#define SCB_DCISW_SET_Pos   5U

SCB DCISW: Set Position

◆ SCB_DCISW_SET_Pos [4/8]

#define SCB_DCISW_SET_Pos   5U

SCB DCISW: Set Position

◆ SCB_DCISW_SET_Pos [5/8]

#define SCB_DCISW_SET_Pos   5U

SCB DCISW: Set Position

◆ SCB_DCISW_SET_Pos [6/8]

#define SCB_DCISW_SET_Pos   5U

SCB DCISW: Set Position

◆ SCB_DCISW_SET_Pos [7/8]

#define SCB_DCISW_SET_Pos   5U

SCB DCISW: Set Position

◆ SCB_DCISW_SET_Pos [8/8]

#define SCB_DCISW_SET_Pos   5U

SCB DCISW: Set Position

◆ SCB_DCISW_WAY_Msk [1/8]

#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

◆ SCB_DCISW_WAY_Msk [2/8]

#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

◆ SCB_DCISW_WAY_Msk [3/8]

#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

◆ SCB_DCISW_WAY_Msk [4/8]

#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

◆ SCB_DCISW_WAY_Msk [5/8]

#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

◆ SCB_DCISW_WAY_Msk [6/8]

#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

◆ SCB_DCISW_WAY_Msk [7/8]

#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

◆ SCB_DCISW_WAY_Msk [8/8]

#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

◆ SCB_DCISW_WAY_Pos [1/8]

#define SCB_DCISW_WAY_Pos   30U

SCB DCISW: Way Position

◆ SCB_DCISW_WAY_Pos [2/8]

#define SCB_DCISW_WAY_Pos   30U

SCB DCISW: Way Position

◆ SCB_DCISW_WAY_Pos [3/8]

#define SCB_DCISW_WAY_Pos   30U

SCB DCISW: Way Position

◆ SCB_DCISW_WAY_Pos [4/8]

#define SCB_DCISW_WAY_Pos   30U

SCB DCISW: Way Position

◆ SCB_DCISW_WAY_Pos [5/8]

#define SCB_DCISW_WAY_Pos   30U

SCB DCISW: Way Position

◆ SCB_DCISW_WAY_Pos [6/8]

#define SCB_DCISW_WAY_Pos   30U

SCB DCISW: Way Position

◆ SCB_DCISW_WAY_Pos [7/8]

#define SCB_DCISW_WAY_Pos   30U

SCB DCISW: Way Position

◆ SCB_DCISW_WAY_Pos [8/8]

#define SCB_DCISW_WAY_Pos   30U

SCB DCISW: Way Position

◆ SCB_DFSR_BKPT_Msk [1/11]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

◆ SCB_DFSR_BKPT_Msk [2/11]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

◆ SCB_DFSR_BKPT_Msk [3/11]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

◆ SCB_DFSR_BKPT_Msk [4/11]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

◆ SCB_DFSR_BKPT_Msk [5/11]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

◆ SCB_DFSR_BKPT_Msk [6/11]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

◆ SCB_DFSR_BKPT_Msk [7/11]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

◆ SCB_DFSR_BKPT_Msk [8/11]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

◆ SCB_DFSR_BKPT_Msk [9/11]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

◆ SCB_DFSR_BKPT_Msk [10/11]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

◆ SCB_DFSR_BKPT_Msk [11/11]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

◆ SCB_DFSR_BKPT_Pos [1/11]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

◆ SCB_DFSR_BKPT_Pos [2/11]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

◆ SCB_DFSR_BKPT_Pos [3/11]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

◆ SCB_DFSR_BKPT_Pos [4/11]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

◆ SCB_DFSR_BKPT_Pos [5/11]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

◆ SCB_DFSR_BKPT_Pos [6/11]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

◆ SCB_DFSR_BKPT_Pos [7/11]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

◆ SCB_DFSR_BKPT_Pos [8/11]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

◆ SCB_DFSR_BKPT_Pos [9/11]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

◆ SCB_DFSR_BKPT_Pos [10/11]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

◆ SCB_DFSR_BKPT_Pos [11/11]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

◆ SCB_DFSR_DWTTRAP_Msk [1/11]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

◆ SCB_DFSR_DWTTRAP_Msk [2/11]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

◆ SCB_DFSR_DWTTRAP_Msk [3/11]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

◆ SCB_DFSR_DWTTRAP_Msk [4/11]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

◆ SCB_DFSR_DWTTRAP_Msk [5/11]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

◆ SCB_DFSR_DWTTRAP_Msk [6/11]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

◆ SCB_DFSR_DWTTRAP_Msk [7/11]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

◆ SCB_DFSR_DWTTRAP_Msk [8/11]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

◆ SCB_DFSR_DWTTRAP_Msk [9/11]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

◆ SCB_DFSR_DWTTRAP_Msk [10/11]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

◆ SCB_DFSR_DWTTRAP_Msk [11/11]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

◆ SCB_DFSR_DWTTRAP_Pos [1/11]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

◆ SCB_DFSR_DWTTRAP_Pos [2/11]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

◆ SCB_DFSR_DWTTRAP_Pos [3/11]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

◆ SCB_DFSR_DWTTRAP_Pos [4/11]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

◆ SCB_DFSR_DWTTRAP_Pos [5/11]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

◆ SCB_DFSR_DWTTRAP_Pos [6/11]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

◆ SCB_DFSR_DWTTRAP_Pos [7/11]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

◆ SCB_DFSR_DWTTRAP_Pos [8/11]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

◆ SCB_DFSR_DWTTRAP_Pos [9/11]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

◆ SCB_DFSR_DWTTRAP_Pos [10/11]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

◆ SCB_DFSR_DWTTRAP_Pos [11/11]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

◆ SCB_DFSR_EXTERNAL_Msk [1/11]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

◆ SCB_DFSR_EXTERNAL_Msk [2/11]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

◆ SCB_DFSR_EXTERNAL_Msk [3/11]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

◆ SCB_DFSR_EXTERNAL_Msk [4/11]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

◆ SCB_DFSR_EXTERNAL_Msk [5/11]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

◆ SCB_DFSR_EXTERNAL_Msk [6/11]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

◆ SCB_DFSR_EXTERNAL_Msk [7/11]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

◆ SCB_DFSR_EXTERNAL_Msk [8/11]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

◆ SCB_DFSR_EXTERNAL_Msk [9/11]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

◆ SCB_DFSR_EXTERNAL_Msk [10/11]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

◆ SCB_DFSR_EXTERNAL_Msk [11/11]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

◆ SCB_DFSR_EXTERNAL_Pos [1/11]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

◆ SCB_DFSR_EXTERNAL_Pos [2/11]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

◆ SCB_DFSR_EXTERNAL_Pos [3/11]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

◆ SCB_DFSR_EXTERNAL_Pos [4/11]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

◆ SCB_DFSR_EXTERNAL_Pos [5/11]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

◆ SCB_DFSR_EXTERNAL_Pos [6/11]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

◆ SCB_DFSR_EXTERNAL_Pos [7/11]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

◆ SCB_DFSR_EXTERNAL_Pos [8/11]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

◆ SCB_DFSR_EXTERNAL_Pos [9/11]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

◆ SCB_DFSR_EXTERNAL_Pos [10/11]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

◆ SCB_DFSR_EXTERNAL_Pos [11/11]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

◆ SCB_DFSR_HALTED_Msk [1/11]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

◆ SCB_DFSR_HALTED_Msk [2/11]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

◆ SCB_DFSR_HALTED_Msk [3/11]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

◆ SCB_DFSR_HALTED_Msk [4/11]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

◆ SCB_DFSR_HALTED_Msk [5/11]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

◆ SCB_DFSR_HALTED_Msk [6/11]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

◆ SCB_DFSR_HALTED_Msk [7/11]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

◆ SCB_DFSR_HALTED_Msk [8/11]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

◆ SCB_DFSR_HALTED_Msk [9/11]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

◆ SCB_DFSR_HALTED_Msk [10/11]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

◆ SCB_DFSR_HALTED_Msk [11/11]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

◆ SCB_DFSR_HALTED_Pos [1/11]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

◆ SCB_DFSR_HALTED_Pos [2/11]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

◆ SCB_DFSR_HALTED_Pos [3/11]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

◆ SCB_DFSR_HALTED_Pos [4/11]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

◆ SCB_DFSR_HALTED_Pos [5/11]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

◆ SCB_DFSR_HALTED_Pos [6/11]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

◆ SCB_DFSR_HALTED_Pos [7/11]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

◆ SCB_DFSR_HALTED_Pos [8/11]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

◆ SCB_DFSR_HALTED_Pos [9/11]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

◆ SCB_DFSR_HALTED_Pos [10/11]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

◆ SCB_DFSR_HALTED_Pos [11/11]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

◆ SCB_DFSR_PMU_Msk [1/3]

#define SCB_DFSR_PMU_Msk   (1UL << SCB_DFSR_PMU_Pos)

SCB DFSR: PMU Mask

◆ SCB_DFSR_PMU_Msk [2/3]

#define SCB_DFSR_PMU_Msk   (1UL << SCB_DFSR_PMU_Pos)

SCB DFSR: PMU Mask

◆ SCB_DFSR_PMU_Msk [3/3]

#define SCB_DFSR_PMU_Msk   (1UL << SCB_DFSR_PMU_Pos)

SCB DFSR: PMU Mask

◆ SCB_DFSR_PMU_Pos [1/3]

#define SCB_DFSR_PMU_Pos   5U

SCB DFSR: PMU Position

◆ SCB_DFSR_PMU_Pos [2/3]

#define SCB_DFSR_PMU_Pos   5U

SCB DFSR: PMU Position

◆ SCB_DFSR_PMU_Pos [3/3]

#define SCB_DFSR_PMU_Pos   5U

SCB DFSR: PMU Position

◆ SCB_DFSR_VCATCH_Msk [1/11]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

◆ SCB_DFSR_VCATCH_Msk [2/11]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

◆ SCB_DFSR_VCATCH_Msk [3/11]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

◆ SCB_DFSR_VCATCH_Msk [4/11]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

◆ SCB_DFSR_VCATCH_Msk [5/11]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

◆ SCB_DFSR_VCATCH_Msk [6/11]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

◆ SCB_DFSR_VCATCH_Msk [7/11]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

◆ SCB_DFSR_VCATCH_Msk [8/11]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

◆ SCB_DFSR_VCATCH_Msk [9/11]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

◆ SCB_DFSR_VCATCH_Msk [10/11]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

◆ SCB_DFSR_VCATCH_Msk [11/11]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

◆ SCB_DFSR_VCATCH_Pos [1/11]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

◆ SCB_DFSR_VCATCH_Pos [2/11]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

◆ SCB_DFSR_VCATCH_Pos [3/11]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

◆ SCB_DFSR_VCATCH_Pos [4/11]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

◆ SCB_DFSR_VCATCH_Pos [5/11]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

◆ SCB_DFSR_VCATCH_Pos [6/11]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

◆ SCB_DFSR_VCATCH_Pos [7/11]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

◆ SCB_DFSR_VCATCH_Pos [8/11]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

◆ SCB_DFSR_VCATCH_Pos [9/11]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

◆ SCB_DFSR_VCATCH_Pos [10/11]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

◆ SCB_DFSR_VCATCH_Pos [11/11]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

◆ SCB_DTCMCR_EN_Msk [1/2]

#define SCB_DTCMCR_EN_Msk   (1UL /*<< SCB_DTCMCR_EN_Pos*/)

SCB DTCMCR: EN Mask

◆ SCB_DTCMCR_EN_Msk [2/2]

#define SCB_DTCMCR_EN_Msk   (1UL /*<< SCB_DTCMCR_EN_Pos*/)

SCB DTCMCR: EN Mask

◆ SCB_DTCMCR_EN_Pos [1/2]

#define SCB_DTCMCR_EN_Pos   0U

SCB DTCMCR: EN Position

◆ SCB_DTCMCR_EN_Pos [2/2]

#define SCB_DTCMCR_EN_Pos   0U

SCB DTCMCR: EN Position

◆ SCB_DTCMCR_RETEN_Msk

#define SCB_DTCMCR_RETEN_Msk   (1UL << SCB_DTCMCR_RETEN_Pos)

SCB DTCMCR: RETEN Mask

◆ SCB_DTCMCR_RETEN_Pos

#define SCB_DTCMCR_RETEN_Pos   2U

SCB DTCMCR: RETEN Position

◆ SCB_DTCMCR_RMW_Msk

#define SCB_DTCMCR_RMW_Msk   (1UL << SCB_DTCMCR_RMW_Pos)

SCB DTCMCR: RMW Mask

◆ SCB_DTCMCR_RMW_Pos

#define SCB_DTCMCR_RMW_Pos   1U

SCB DTCMCR: RMW Position

◆ SCB_DTCMCR_SZ_Msk [1/2]

#define SCB_DTCMCR_SZ_Msk   (0xFUL << SCB_DTCMCR_SZ_Pos)

SCB DTCMCR: SZ Mask

◆ SCB_DTCMCR_SZ_Msk [2/2]

#define SCB_DTCMCR_SZ_Msk   (0xFUL << SCB_DTCMCR_SZ_Pos)

SCB DTCMCR: SZ Mask

◆ SCB_DTCMCR_SZ_Pos [1/2]

#define SCB_DTCMCR_SZ_Pos   3U

SCB DTCMCR: SZ Position

◆ SCB_DTCMCR_SZ_Pos [2/2]

#define SCB_DTCMCR_SZ_Pos   3U

SCB DTCMCR: SZ Position

◆ SCB_HFSR_DEBUGEVT_Msk [1/11]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

◆ SCB_HFSR_DEBUGEVT_Msk [2/11]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

◆ SCB_HFSR_DEBUGEVT_Msk [3/11]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

◆ SCB_HFSR_DEBUGEVT_Msk [4/11]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

◆ SCB_HFSR_DEBUGEVT_Msk [5/11]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

◆ SCB_HFSR_DEBUGEVT_Msk [6/11]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

◆ SCB_HFSR_DEBUGEVT_Msk [7/11]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

◆ SCB_HFSR_DEBUGEVT_Msk [8/11]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

◆ SCB_HFSR_DEBUGEVT_Msk [9/11]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

◆ SCB_HFSR_DEBUGEVT_Msk [10/11]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

◆ SCB_HFSR_DEBUGEVT_Msk [11/11]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

◆ SCB_HFSR_DEBUGEVT_Pos [1/11]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

◆ SCB_HFSR_DEBUGEVT_Pos [2/11]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

◆ SCB_HFSR_DEBUGEVT_Pos [3/11]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

◆ SCB_HFSR_DEBUGEVT_Pos [4/11]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

◆ SCB_HFSR_DEBUGEVT_Pos [5/11]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

◆ SCB_HFSR_DEBUGEVT_Pos [6/11]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

◆ SCB_HFSR_DEBUGEVT_Pos [7/11]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

◆ SCB_HFSR_DEBUGEVT_Pos [8/11]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

◆ SCB_HFSR_DEBUGEVT_Pos [9/11]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

◆ SCB_HFSR_DEBUGEVT_Pos [10/11]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

◆ SCB_HFSR_DEBUGEVT_Pos [11/11]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

◆ SCB_HFSR_FORCED_Msk [1/11]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

◆ SCB_HFSR_FORCED_Msk [2/11]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

◆ SCB_HFSR_FORCED_Msk [3/11]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

◆ SCB_HFSR_FORCED_Msk [4/11]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

◆ SCB_HFSR_FORCED_Msk [5/11]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

◆ SCB_HFSR_FORCED_Msk [6/11]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

◆ SCB_HFSR_FORCED_Msk [7/11]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

◆ SCB_HFSR_FORCED_Msk [8/11]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

◆ SCB_HFSR_FORCED_Msk [9/11]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

◆ SCB_HFSR_FORCED_Msk [10/11]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

◆ SCB_HFSR_FORCED_Msk [11/11]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

◆ SCB_HFSR_FORCED_Pos [1/11]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

◆ SCB_HFSR_FORCED_Pos [2/11]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

◆ SCB_HFSR_FORCED_Pos [3/11]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

◆ SCB_HFSR_FORCED_Pos [4/11]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

◆ SCB_HFSR_FORCED_Pos [5/11]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

◆ SCB_HFSR_FORCED_Pos [6/11]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

◆ SCB_HFSR_FORCED_Pos [7/11]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

◆ SCB_HFSR_FORCED_Pos [8/11]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

◆ SCB_HFSR_FORCED_Pos [9/11]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

◆ SCB_HFSR_FORCED_Pos [10/11]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

◆ SCB_HFSR_FORCED_Pos [11/11]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

◆ SCB_HFSR_VECTTBL_Msk [1/11]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

◆ SCB_HFSR_VECTTBL_Msk [2/11]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

◆ SCB_HFSR_VECTTBL_Msk [3/11]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

◆ SCB_HFSR_VECTTBL_Msk [4/11]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

◆ SCB_HFSR_VECTTBL_Msk [5/11]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

◆ SCB_HFSR_VECTTBL_Msk [6/11]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

◆ SCB_HFSR_VECTTBL_Msk [7/11]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

◆ SCB_HFSR_VECTTBL_Msk [8/11]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

◆ SCB_HFSR_VECTTBL_Msk [9/11]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

◆ SCB_HFSR_VECTTBL_Msk [10/11]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

◆ SCB_HFSR_VECTTBL_Msk [11/11]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

◆ SCB_HFSR_VECTTBL_Pos [1/11]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

◆ SCB_HFSR_VECTTBL_Pos [2/11]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

◆ SCB_HFSR_VECTTBL_Pos [3/11]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

◆ SCB_HFSR_VECTTBL_Pos [4/11]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

◆ SCB_HFSR_VECTTBL_Pos [5/11]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

◆ SCB_HFSR_VECTTBL_Pos [6/11]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

◆ SCB_HFSR_VECTTBL_Pos [7/11]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

◆ SCB_HFSR_VECTTBL_Pos [8/11]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

◆ SCB_HFSR_VECTTBL_Pos [9/11]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

◆ SCB_HFSR_VECTTBL_Pos [10/11]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

◆ SCB_HFSR_VECTTBL_Pos [11/11]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

◆ SCB_ICSR_ISRPENDING_Msk [1/17]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

◆ SCB_ICSR_ISRPENDING_Msk [2/17]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

◆ SCB_ICSR_ISRPENDING_Msk [3/17]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

◆ SCB_ICSR_ISRPENDING_Msk [4/17]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

◆ SCB_ICSR_ISRPENDING_Msk [5/17]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

◆ SCB_ICSR_ISRPENDING_Msk [6/17]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

◆ SCB_ICSR_ISRPENDING_Msk [7/17]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

◆ SCB_ICSR_ISRPENDING_Msk [8/17]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

◆ SCB_ICSR_ISRPENDING_Msk [9/17]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

◆ SCB_ICSR_ISRPENDING_Msk [10/17]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

◆ SCB_ICSR_ISRPENDING_Msk [11/17]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

◆ SCB_ICSR_ISRPENDING_Msk [12/17]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

◆ SCB_ICSR_ISRPENDING_Msk [13/17]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

◆ SCB_ICSR_ISRPENDING_Msk [14/17]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

◆ SCB_ICSR_ISRPENDING_Msk [15/17]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

◆ SCB_ICSR_ISRPENDING_Msk [16/17]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

◆ SCB_ICSR_ISRPENDING_Msk [17/17]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

◆ SCB_ICSR_ISRPENDING_Pos [1/17]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

◆ SCB_ICSR_ISRPENDING_Pos [2/17]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

◆ SCB_ICSR_ISRPENDING_Pos [3/17]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

◆ SCB_ICSR_ISRPENDING_Pos [4/17]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

◆ SCB_ICSR_ISRPENDING_Pos [5/17]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

◆ SCB_ICSR_ISRPENDING_Pos [6/17]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

◆ SCB_ICSR_ISRPENDING_Pos [7/17]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

◆ SCB_ICSR_ISRPENDING_Pos [8/17]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

◆ SCB_ICSR_ISRPENDING_Pos [9/17]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

◆ SCB_ICSR_ISRPENDING_Pos [10/17]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

◆ SCB_ICSR_ISRPENDING_Pos [11/17]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

◆ SCB_ICSR_ISRPENDING_Pos [12/17]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

◆ SCB_ICSR_ISRPENDING_Pos [13/17]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

◆ SCB_ICSR_ISRPENDING_Pos [14/17]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

◆ SCB_ICSR_ISRPENDING_Pos [15/17]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

◆ SCB_ICSR_ISRPENDING_Pos [16/17]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

◆ SCB_ICSR_ISRPENDING_Pos [17/17]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

◆ SCB_ICSR_ISRPREEMPT_Msk [1/17]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

◆ SCB_ICSR_ISRPREEMPT_Msk [2/17]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

◆ SCB_ICSR_ISRPREEMPT_Msk [3/17]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

◆ SCB_ICSR_ISRPREEMPT_Msk [4/17]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

◆ SCB_ICSR_ISRPREEMPT_Msk [5/17]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

◆ SCB_ICSR_ISRPREEMPT_Msk [6/17]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

◆ SCB_ICSR_ISRPREEMPT_Msk [7/17]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

◆ SCB_ICSR_ISRPREEMPT_Msk [8/17]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

◆ SCB_ICSR_ISRPREEMPT_Msk [9/17]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

◆ SCB_ICSR_ISRPREEMPT_Msk [10/17]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

◆ SCB_ICSR_ISRPREEMPT_Msk [11/17]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

◆ SCB_ICSR_ISRPREEMPT_Msk [12/17]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

◆ SCB_ICSR_ISRPREEMPT_Msk [13/17]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

◆ SCB_ICSR_ISRPREEMPT_Msk [14/17]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

◆ SCB_ICSR_ISRPREEMPT_Msk [15/17]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

◆ SCB_ICSR_ISRPREEMPT_Msk [16/17]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

◆ SCB_ICSR_ISRPREEMPT_Msk [17/17]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

◆ SCB_ICSR_ISRPREEMPT_Pos [1/17]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

◆ SCB_ICSR_ISRPREEMPT_Pos [2/17]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

◆ SCB_ICSR_ISRPREEMPT_Pos [3/17]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

◆ SCB_ICSR_ISRPREEMPT_Pos [4/17]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

◆ SCB_ICSR_ISRPREEMPT_Pos [5/17]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

◆ SCB_ICSR_ISRPREEMPT_Pos [6/17]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

◆ SCB_ICSR_ISRPREEMPT_Pos [7/17]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

◆ SCB_ICSR_ISRPREEMPT_Pos [8/17]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

◆ SCB_ICSR_ISRPREEMPT_Pos [9/17]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

◆ SCB_ICSR_ISRPREEMPT_Pos [10/17]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

◆ SCB_ICSR_ISRPREEMPT_Pos [11/17]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

◆ SCB_ICSR_ISRPREEMPT_Pos [12/17]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

◆ SCB_ICSR_ISRPREEMPT_Pos [13/17]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

◆ SCB_ICSR_ISRPREEMPT_Pos [14/17]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

◆ SCB_ICSR_ISRPREEMPT_Pos [15/17]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

◆ SCB_ICSR_ISRPREEMPT_Pos [16/17]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

◆ SCB_ICSR_ISRPREEMPT_Pos [17/17]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

◆ SCB_ICSR_NMIPENDSET_Msk [1/17]

#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

SCB ICSR: NMIPENDSET Mask

◆ SCB_ICSR_NMIPENDSET_Msk [2/17]

#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

SCB ICSR: NMIPENDSET Mask

◆ SCB_ICSR_NMIPENDSET_Msk [3/17]

#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

SCB ICSR: NMIPENDSET Mask

◆ SCB_ICSR_NMIPENDSET_Msk [4/17]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

SCB ICSR: NMIPENDSET Mask, backward compatibility

◆ SCB_ICSR_NMIPENDSET_Msk [5/17]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

SCB ICSR: NMIPENDSET Mask, backward compatibility

◆ SCB_ICSR_NMIPENDSET_Msk [6/17]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

SCB ICSR: NMIPENDSET Mask, backward compatibility

◆ SCB_ICSR_NMIPENDSET_Msk [7/17]

#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

SCB ICSR: NMIPENDSET Mask

◆ SCB_ICSR_NMIPENDSET_Msk [8/17]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

SCB ICSR: NMIPENDSET Mask, backward compatibility

◆ SCB_ICSR_NMIPENDSET_Msk [9/17]

#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

SCB ICSR: NMIPENDSET Mask

◆ SCB_ICSR_NMIPENDSET_Msk [10/17]

#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

SCB ICSR: NMIPENDSET Mask

◆ SCB_ICSR_NMIPENDSET_Msk [11/17]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

SCB ICSR: NMIPENDSET Mask, backward compatibility

◆ SCB_ICSR_NMIPENDSET_Msk [12/17]

#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

SCB ICSR: NMIPENDSET Mask

◆ SCB_ICSR_NMIPENDSET_Msk [13/17]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

SCB ICSR: NMIPENDSET Mask, backward compatibility

◆ SCB_ICSR_NMIPENDSET_Msk [14/17]

#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

SCB ICSR: NMIPENDSET Mask

◆ SCB_ICSR_NMIPENDSET_Msk [15/17]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

SCB ICSR: NMIPENDSET Mask, backward compatibility

◆ SCB_ICSR_NMIPENDSET_Msk [16/17]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

SCB ICSR: NMIPENDSET Mask, backward compatibility

◆ SCB_ICSR_NMIPENDSET_Msk [17/17]

#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

◆ SCB_ICSR_NMIPENDSET_Pos [1/17]

#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

SCB ICSR: NMIPENDSET Position

◆ SCB_ICSR_NMIPENDSET_Pos [2/17]

#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

SCB ICSR: NMIPENDSET Position

◆ SCB_ICSR_NMIPENDSET_Pos [3/17]

#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

SCB ICSR: NMIPENDSET Position

◆ SCB_ICSR_NMIPENDSET_Pos [4/17]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

SCB ICSR: NMIPENDSET Position, backward compatibility

◆ SCB_ICSR_NMIPENDSET_Pos [5/17]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

SCB ICSR: NMIPENDSET Position, backward compatibility

◆ SCB_ICSR_NMIPENDSET_Pos [6/17]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

SCB ICSR: NMIPENDSET Position, backward compatibility

◆ SCB_ICSR_NMIPENDSET_Pos [7/17]

#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

SCB ICSR: NMIPENDSET Position

◆ SCB_ICSR_NMIPENDSET_Pos [8/17]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

SCB ICSR: NMIPENDSET Position, backward compatibility

◆ SCB_ICSR_NMIPENDSET_Pos [9/17]

#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

SCB ICSR: NMIPENDSET Position

◆ SCB_ICSR_NMIPENDSET_Pos [10/17]

#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

SCB ICSR: NMIPENDSET Position

◆ SCB_ICSR_NMIPENDSET_Pos [11/17]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

SCB ICSR: NMIPENDSET Position, backward compatibility

◆ SCB_ICSR_NMIPENDSET_Pos [12/17]

#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

SCB ICSR: NMIPENDSET Position

◆ SCB_ICSR_NMIPENDSET_Pos [13/17]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

SCB ICSR: NMIPENDSET Position, backward compatibility

◆ SCB_ICSR_NMIPENDSET_Pos [14/17]

#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

SCB ICSR: NMIPENDSET Position

◆ SCB_ICSR_NMIPENDSET_Pos [15/17]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

SCB ICSR: NMIPENDSET Position, backward compatibility

◆ SCB_ICSR_NMIPENDSET_Pos [16/17]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

SCB ICSR: NMIPENDSET Position, backward compatibility

◆ SCB_ICSR_NMIPENDSET_Pos [17/17]

#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

◆ SCB_ICSR_PENDNMICLR_Msk [1/9]

#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

◆ SCB_ICSR_PENDNMICLR_Msk [2/9]

#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

◆ SCB_ICSR_PENDNMICLR_Msk [3/9]

#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

◆ SCB_ICSR_PENDNMICLR_Msk [4/9]

#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

◆ SCB_ICSR_PENDNMICLR_Msk [5/9]

#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

◆ SCB_ICSR_PENDNMICLR_Msk [6/9]

#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

◆ SCB_ICSR_PENDNMICLR_Msk [7/9]

#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

◆ SCB_ICSR_PENDNMICLR_Msk [8/9]

#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

◆ SCB_ICSR_PENDNMICLR_Msk [9/9]

#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

◆ SCB_ICSR_PENDNMICLR_Pos [1/9]

#define SCB_ICSR_PENDNMICLR_Pos   30U

SCB ICSR: PENDNMICLR Position

◆ SCB_ICSR_PENDNMICLR_Pos [2/9]

#define SCB_ICSR_PENDNMICLR_Pos   30U

SCB ICSR: PENDNMICLR Position

◆ SCB_ICSR_PENDNMICLR_Pos [3/9]

#define SCB_ICSR_PENDNMICLR_Pos   30U

SCB ICSR: PENDNMICLR Position

◆ SCB_ICSR_PENDNMICLR_Pos [4/9]

#define SCB_ICSR_PENDNMICLR_Pos   30U

SCB ICSR: PENDNMICLR Position

◆ SCB_ICSR_PENDNMICLR_Pos [5/9]

#define SCB_ICSR_PENDNMICLR_Pos   30U

SCB ICSR: PENDNMICLR Position

◆ SCB_ICSR_PENDNMICLR_Pos [6/9]

#define SCB_ICSR_PENDNMICLR_Pos   30U

SCB ICSR: PENDNMICLR Position

◆ SCB_ICSR_PENDNMICLR_Pos [7/9]

#define SCB_ICSR_PENDNMICLR_Pos   30U

SCB ICSR: PENDNMICLR Position

◆ SCB_ICSR_PENDNMICLR_Pos [8/9]

#define SCB_ICSR_PENDNMICLR_Pos   30U

SCB ICSR: PENDNMICLR Position

◆ SCB_ICSR_PENDNMICLR_Pos [9/9]

#define SCB_ICSR_PENDNMICLR_Pos   30U

SCB ICSR: PENDNMICLR Position

◆ SCB_ICSR_PENDNMISET_Msk [1/9]

#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

◆ SCB_ICSR_PENDNMISET_Msk [2/9]

#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

◆ SCB_ICSR_PENDNMISET_Msk [3/9]

#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

◆ SCB_ICSR_PENDNMISET_Msk [4/9]

#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

◆ SCB_ICSR_PENDNMISET_Msk [5/9]

#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

◆ SCB_ICSR_PENDNMISET_Msk [6/9]

#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

◆ SCB_ICSR_PENDNMISET_Msk [7/9]

#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

◆ SCB_ICSR_PENDNMISET_Msk [8/9]

#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

◆ SCB_ICSR_PENDNMISET_Msk [9/9]

#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

◆ SCB_ICSR_PENDNMISET_Pos [1/9]

#define SCB_ICSR_PENDNMISET_Pos   31U

SCB ICSR: PENDNMISET Position

◆ SCB_ICSR_PENDNMISET_Pos [2/9]

#define SCB_ICSR_PENDNMISET_Pos   31U

SCB ICSR: PENDNMISET Position

◆ SCB_ICSR_PENDNMISET_Pos [3/9]

#define SCB_ICSR_PENDNMISET_Pos   31U

SCB ICSR: PENDNMISET Position

◆ SCB_ICSR_PENDNMISET_Pos [4/9]

#define SCB_ICSR_PENDNMISET_Pos   31U

SCB ICSR: PENDNMISET Position

◆ SCB_ICSR_PENDNMISET_Pos [5/9]

#define SCB_ICSR_PENDNMISET_Pos   31U

SCB ICSR: PENDNMISET Position

◆ SCB_ICSR_PENDNMISET_Pos [6/9]

#define SCB_ICSR_PENDNMISET_Pos   31U

SCB ICSR: PENDNMISET Position

◆ SCB_ICSR_PENDNMISET_Pos [7/9]

#define SCB_ICSR_PENDNMISET_Pos   31U

SCB ICSR: PENDNMISET Position

◆ SCB_ICSR_PENDNMISET_Pos [8/9]

#define SCB_ICSR_PENDNMISET_Pos   31U

SCB ICSR: PENDNMISET Position

◆ SCB_ICSR_PENDNMISET_Pos [9/9]

#define SCB_ICSR_PENDNMISET_Pos   31U

SCB ICSR: PENDNMISET Position

◆ SCB_ICSR_PENDSTCLR_Msk [1/17]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

◆ SCB_ICSR_PENDSTCLR_Msk [2/17]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

◆ SCB_ICSR_PENDSTCLR_Msk [3/17]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

◆ SCB_ICSR_PENDSTCLR_Msk [4/17]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

◆ SCB_ICSR_PENDSTCLR_Msk [5/17]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

◆ SCB_ICSR_PENDSTCLR_Msk [6/17]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

◆ SCB_ICSR_PENDSTCLR_Msk [7/17]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

◆ SCB_ICSR_PENDSTCLR_Msk [8/17]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

◆ SCB_ICSR_PENDSTCLR_Msk [9/17]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

◆ SCB_ICSR_PENDSTCLR_Msk [10/17]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

◆ SCB_ICSR_PENDSTCLR_Msk [11/17]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

◆ SCB_ICSR_PENDSTCLR_Msk [12/17]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

◆ SCB_ICSR_PENDSTCLR_Msk [13/17]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

◆ SCB_ICSR_PENDSTCLR_Msk [14/17]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

◆ SCB_ICSR_PENDSTCLR_Msk [15/17]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

◆ SCB_ICSR_PENDSTCLR_Msk [16/17]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

◆ SCB_ICSR_PENDSTCLR_Msk [17/17]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

◆ SCB_ICSR_PENDSTCLR_Pos [1/17]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

◆ SCB_ICSR_PENDSTCLR_Pos [2/17]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

◆ SCB_ICSR_PENDSTCLR_Pos [3/17]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

◆ SCB_ICSR_PENDSTCLR_Pos [4/17]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

◆ SCB_ICSR_PENDSTCLR_Pos [5/17]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

◆ SCB_ICSR_PENDSTCLR_Pos [6/17]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

◆ SCB_ICSR_PENDSTCLR_Pos [7/17]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

◆ SCB_ICSR_PENDSTCLR_Pos [8/17]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

◆ SCB_ICSR_PENDSTCLR_Pos [9/17]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

◆ SCB_ICSR_PENDSTCLR_Pos [10/17]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

◆ SCB_ICSR_PENDSTCLR_Pos [11/17]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

◆ SCB_ICSR_PENDSTCLR_Pos [12/17]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

◆ SCB_ICSR_PENDSTCLR_Pos [13/17]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

◆ SCB_ICSR_PENDSTCLR_Pos [14/17]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

◆ SCB_ICSR_PENDSTCLR_Pos [15/17]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

◆ SCB_ICSR_PENDSTCLR_Pos [16/17]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

◆ SCB_ICSR_PENDSTCLR_Pos [17/17]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

◆ SCB_ICSR_PENDSTSET_Msk [1/17]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

◆ SCB_ICSR_PENDSTSET_Msk [2/17]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

◆ SCB_ICSR_PENDSTSET_Msk [3/17]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

◆ SCB_ICSR_PENDSTSET_Msk [4/17]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

◆ SCB_ICSR_PENDSTSET_Msk [5/17]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

◆ SCB_ICSR_PENDSTSET_Msk [6/17]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

◆ SCB_ICSR_PENDSTSET_Msk [7/17]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

◆ SCB_ICSR_PENDSTSET_Msk [8/17]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

◆ SCB_ICSR_PENDSTSET_Msk [9/17]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

◆ SCB_ICSR_PENDSTSET_Msk [10/17]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

◆ SCB_ICSR_PENDSTSET_Msk [11/17]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

◆ SCB_ICSR_PENDSTSET_Msk [12/17]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

◆ SCB_ICSR_PENDSTSET_Msk [13/17]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

◆ SCB_ICSR_PENDSTSET_Msk [14/17]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

◆ SCB_ICSR_PENDSTSET_Msk [15/17]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

◆ SCB_ICSR_PENDSTSET_Msk [16/17]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

◆ SCB_ICSR_PENDSTSET_Msk [17/17]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

◆ SCB_ICSR_PENDSTSET_Pos [1/17]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

◆ SCB_ICSR_PENDSTSET_Pos [2/17]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

◆ SCB_ICSR_PENDSTSET_Pos [3/17]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

◆ SCB_ICSR_PENDSTSET_Pos [4/17]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

◆ SCB_ICSR_PENDSTSET_Pos [5/17]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

◆ SCB_ICSR_PENDSTSET_Pos [6/17]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

◆ SCB_ICSR_PENDSTSET_Pos [7/17]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

◆ SCB_ICSR_PENDSTSET_Pos [8/17]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

◆ SCB_ICSR_PENDSTSET_Pos [9/17]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

◆ SCB_ICSR_PENDSTSET_Pos [10/17]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

◆ SCB_ICSR_PENDSTSET_Pos [11/17]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

◆ SCB_ICSR_PENDSTSET_Pos [12/17]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

◆ SCB_ICSR_PENDSTSET_Pos [13/17]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

◆ SCB_ICSR_PENDSTSET_Pos [14/17]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

◆ SCB_ICSR_PENDSTSET_Pos [15/17]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

◆ SCB_ICSR_PENDSTSET_Pos [16/17]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

◆ SCB_ICSR_PENDSTSET_Pos [17/17]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

◆ SCB_ICSR_PENDSVCLR_Msk [1/17]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

◆ SCB_ICSR_PENDSVCLR_Msk [2/17]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

◆ SCB_ICSR_PENDSVCLR_Msk [3/17]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

◆ SCB_ICSR_PENDSVCLR_Msk [4/17]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

◆ SCB_ICSR_PENDSVCLR_Msk [5/17]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

◆ SCB_ICSR_PENDSVCLR_Msk [6/17]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

◆ SCB_ICSR_PENDSVCLR_Msk [7/17]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

◆ SCB_ICSR_PENDSVCLR_Msk [8/17]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

◆ SCB_ICSR_PENDSVCLR_Msk [9/17]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

◆ SCB_ICSR_PENDSVCLR_Msk [10/17]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

◆ SCB_ICSR_PENDSVCLR_Msk [11/17]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

◆ SCB_ICSR_PENDSVCLR_Msk [12/17]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

◆ SCB_ICSR_PENDSVCLR_Msk [13/17]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

◆ SCB_ICSR_PENDSVCLR_Msk [14/17]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

◆ SCB_ICSR_PENDSVCLR_Msk [15/17]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

◆ SCB_ICSR_PENDSVCLR_Msk [16/17]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

◆ SCB_ICSR_PENDSVCLR_Msk [17/17]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

◆ SCB_ICSR_PENDSVCLR_Pos [1/17]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

◆ SCB_ICSR_PENDSVCLR_Pos [2/17]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

◆ SCB_ICSR_PENDSVCLR_Pos [3/17]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

◆ SCB_ICSR_PENDSVCLR_Pos [4/17]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

◆ SCB_ICSR_PENDSVCLR_Pos [5/17]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

◆ SCB_ICSR_PENDSVCLR_Pos [6/17]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

◆ SCB_ICSR_PENDSVCLR_Pos [7/17]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

◆ SCB_ICSR_PENDSVCLR_Pos [8/17]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

◆ SCB_ICSR_PENDSVCLR_Pos [9/17]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

◆ SCB_ICSR_PENDSVCLR_Pos [10/17]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

◆ SCB_ICSR_PENDSVCLR_Pos [11/17]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

◆ SCB_ICSR_PENDSVCLR_Pos [12/17]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

◆ SCB_ICSR_PENDSVCLR_Pos [13/17]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

◆ SCB_ICSR_PENDSVCLR_Pos [14/17]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

◆ SCB_ICSR_PENDSVCLR_Pos [15/17]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

◆ SCB_ICSR_PENDSVCLR_Pos [16/17]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

◆ SCB_ICSR_PENDSVCLR_Pos [17/17]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

◆ SCB_ICSR_PENDSVSET_Msk [1/17]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

◆ SCB_ICSR_PENDSVSET_Msk [2/17]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

◆ SCB_ICSR_PENDSVSET_Msk [3/17]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

◆ SCB_ICSR_PENDSVSET_Msk [4/17]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

◆ SCB_ICSR_PENDSVSET_Msk [5/17]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

◆ SCB_ICSR_PENDSVSET_Msk [6/17]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

◆ SCB_ICSR_PENDSVSET_Msk [7/17]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

◆ SCB_ICSR_PENDSVSET_Msk [8/17]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

◆ SCB_ICSR_PENDSVSET_Msk [9/17]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

◆ SCB_ICSR_PENDSVSET_Msk [10/17]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

◆ SCB_ICSR_PENDSVSET_Msk [11/17]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

◆ SCB_ICSR_PENDSVSET_Msk [12/17]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

◆ SCB_ICSR_PENDSVSET_Msk [13/17]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

◆ SCB_ICSR_PENDSVSET_Msk [14/17]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

◆ SCB_ICSR_PENDSVSET_Msk [15/17]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

◆ SCB_ICSR_PENDSVSET_Msk [16/17]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

◆ SCB_ICSR_PENDSVSET_Msk [17/17]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

◆ SCB_ICSR_PENDSVSET_Pos [1/17]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

◆ SCB_ICSR_PENDSVSET_Pos [2/17]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

◆ SCB_ICSR_PENDSVSET_Pos [3/17]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

◆ SCB_ICSR_PENDSVSET_Pos [4/17]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

◆ SCB_ICSR_PENDSVSET_Pos [5/17]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

◆ SCB_ICSR_PENDSVSET_Pos [6/17]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

◆ SCB_ICSR_PENDSVSET_Pos [7/17]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

◆ SCB_ICSR_PENDSVSET_Pos [8/17]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

◆ SCB_ICSR_PENDSVSET_Pos [9/17]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

◆ SCB_ICSR_PENDSVSET_Pos [10/17]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

◆ SCB_ICSR_PENDSVSET_Pos [11/17]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

◆ SCB_ICSR_PENDSVSET_Pos [12/17]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

◆ SCB_ICSR_PENDSVSET_Pos [13/17]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

◆ SCB_ICSR_PENDSVSET_Pos [14/17]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

◆ SCB_ICSR_PENDSVSET_Pos [15/17]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

◆ SCB_ICSR_PENDSVSET_Pos [16/17]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

◆ SCB_ICSR_PENDSVSET_Pos [17/17]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

◆ SCB_ICSR_RETTOBASE_Msk [1/13]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

◆ SCB_ICSR_RETTOBASE_Msk [2/13]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

◆ SCB_ICSR_RETTOBASE_Msk [3/13]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

◆ SCB_ICSR_RETTOBASE_Msk [4/13]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

◆ SCB_ICSR_RETTOBASE_Msk [5/13]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

◆ SCB_ICSR_RETTOBASE_Msk [6/13]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

◆ SCB_ICSR_RETTOBASE_Msk [7/13]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

◆ SCB_ICSR_RETTOBASE_Msk [8/13]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

◆ SCB_ICSR_RETTOBASE_Msk [9/13]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

◆ SCB_ICSR_RETTOBASE_Msk [10/13]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

◆ SCB_ICSR_RETTOBASE_Msk [11/13]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

◆ SCB_ICSR_RETTOBASE_Msk [12/13]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

◆ SCB_ICSR_RETTOBASE_Msk [13/13]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

◆ SCB_ICSR_RETTOBASE_Pos [1/13]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

◆ SCB_ICSR_RETTOBASE_Pos [2/13]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

◆ SCB_ICSR_RETTOBASE_Pos [3/13]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

◆ SCB_ICSR_RETTOBASE_Pos [4/13]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

◆ SCB_ICSR_RETTOBASE_Pos [5/13]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

◆ SCB_ICSR_RETTOBASE_Pos [6/13]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

◆ SCB_ICSR_RETTOBASE_Pos [7/13]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

◆ SCB_ICSR_RETTOBASE_Pos [8/13]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

◆ SCB_ICSR_RETTOBASE_Pos [9/13]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

◆ SCB_ICSR_RETTOBASE_Pos [10/13]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

◆ SCB_ICSR_RETTOBASE_Pos [11/13]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

◆ SCB_ICSR_RETTOBASE_Pos [12/13]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

◆ SCB_ICSR_RETTOBASE_Pos [13/13]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

◆ SCB_ICSR_STTNS_Msk [1/9]

#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

◆ SCB_ICSR_STTNS_Msk [2/9]

#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

◆ SCB_ICSR_STTNS_Msk [3/9]

#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

◆ SCB_ICSR_STTNS_Msk [4/9]

#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

◆ SCB_ICSR_STTNS_Msk [5/9]

#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

◆ SCB_ICSR_STTNS_Msk [6/9]

#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

◆ SCB_ICSR_STTNS_Msk [7/9]

#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

◆ SCB_ICSR_STTNS_Msk [8/9]

#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

◆ SCB_ICSR_STTNS_Msk [9/9]

#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

◆ SCB_ICSR_STTNS_Pos [1/9]

#define SCB_ICSR_STTNS_Pos   24U

SCB ICSR: STTNS Position (Security Extension)

◆ SCB_ICSR_STTNS_Pos [2/9]

#define SCB_ICSR_STTNS_Pos   24U

SCB ICSR: STTNS Position (Security Extension)

◆ SCB_ICSR_STTNS_Pos [3/9]

#define SCB_ICSR_STTNS_Pos   24U

SCB ICSR: STTNS Position (Security Extension)

◆ SCB_ICSR_STTNS_Pos [4/9]

#define SCB_ICSR_STTNS_Pos   24U

SCB ICSR: STTNS Position (Security Extension)

◆ SCB_ICSR_STTNS_Pos [5/9]

#define SCB_ICSR_STTNS_Pos   24U

SCB ICSR: STTNS Position (Security Extension)

◆ SCB_ICSR_STTNS_Pos [6/9]

#define SCB_ICSR_STTNS_Pos   24U

SCB ICSR: STTNS Position (Security Extension)

◆ SCB_ICSR_STTNS_Pos [7/9]

#define SCB_ICSR_STTNS_Pos   24U

SCB ICSR: STTNS Position (Security Extension)

◆ SCB_ICSR_STTNS_Pos [8/9]

#define SCB_ICSR_STTNS_Pos   24U

SCB ICSR: STTNS Position (Security Extension)

◆ SCB_ICSR_STTNS_Pos [9/9]

#define SCB_ICSR_STTNS_Pos   24U

SCB ICSR: STTNS Position (Security Extension)

◆ SCB_ICSR_VECTACTIVE_Msk [1/17]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

◆ SCB_ICSR_VECTACTIVE_Msk [2/17]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

◆ SCB_ICSR_VECTACTIVE_Msk [3/17]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

◆ SCB_ICSR_VECTACTIVE_Msk [4/17]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

◆ SCB_ICSR_VECTACTIVE_Msk [5/17]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

◆ SCB_ICSR_VECTACTIVE_Msk [6/17]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

◆ SCB_ICSR_VECTACTIVE_Msk [7/17]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

◆ SCB_ICSR_VECTACTIVE_Msk [8/17]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

◆ SCB_ICSR_VECTACTIVE_Msk [9/17]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

◆ SCB_ICSR_VECTACTIVE_Msk [10/17]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

◆ SCB_ICSR_VECTACTIVE_Msk [11/17]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

◆ SCB_ICSR_VECTACTIVE_Msk [12/17]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

◆ SCB_ICSR_VECTACTIVE_Msk [13/17]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

◆ SCB_ICSR_VECTACTIVE_Msk [14/17]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

◆ SCB_ICSR_VECTACTIVE_Msk [15/17]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

◆ SCB_ICSR_VECTACTIVE_Msk [16/17]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

◆ SCB_ICSR_VECTACTIVE_Msk [17/17]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

◆ SCB_ICSR_VECTACTIVE_Pos [1/17]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

◆ SCB_ICSR_VECTACTIVE_Pos [2/17]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

◆ SCB_ICSR_VECTACTIVE_Pos [3/17]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

◆ SCB_ICSR_VECTACTIVE_Pos [4/17]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

◆ SCB_ICSR_VECTACTIVE_Pos [5/17]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

◆ SCB_ICSR_VECTACTIVE_Pos [6/17]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

◆ SCB_ICSR_VECTACTIVE_Pos [7/17]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

◆ SCB_ICSR_VECTACTIVE_Pos [8/17]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

◆ SCB_ICSR_VECTACTIVE_Pos [9/17]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

◆ SCB_ICSR_VECTACTIVE_Pos [10/17]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

◆ SCB_ICSR_VECTACTIVE_Pos [11/17]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

◆ SCB_ICSR_VECTACTIVE_Pos [12/17]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

◆ SCB_ICSR_VECTACTIVE_Pos [13/17]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

◆ SCB_ICSR_VECTACTIVE_Pos [14/17]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

◆ SCB_ICSR_VECTACTIVE_Pos [15/17]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

◆ SCB_ICSR_VECTACTIVE_Pos [16/17]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

◆ SCB_ICSR_VECTACTIVE_Pos [17/17]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

◆ SCB_ICSR_VECTPENDING_Msk [1/17]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

◆ SCB_ICSR_VECTPENDING_Msk [2/17]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

◆ SCB_ICSR_VECTPENDING_Msk [3/17]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

◆ SCB_ICSR_VECTPENDING_Msk [4/17]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

◆ SCB_ICSR_VECTPENDING_Msk [5/17]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

◆ SCB_ICSR_VECTPENDING_Msk [6/17]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

◆ SCB_ICSR_VECTPENDING_Msk [7/17]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

◆ SCB_ICSR_VECTPENDING_Msk [8/17]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

◆ SCB_ICSR_VECTPENDING_Msk [9/17]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

◆ SCB_ICSR_VECTPENDING_Msk [10/17]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

◆ SCB_ICSR_VECTPENDING_Msk [11/17]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

◆ SCB_ICSR_VECTPENDING_Msk [12/17]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

◆ SCB_ICSR_VECTPENDING_Msk [13/17]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

◆ SCB_ICSR_VECTPENDING_Msk [14/17]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

◆ SCB_ICSR_VECTPENDING_Msk [15/17]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

◆ SCB_ICSR_VECTPENDING_Msk [16/17]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

◆ SCB_ICSR_VECTPENDING_Msk [17/17]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

◆ SCB_ICSR_VECTPENDING_Pos [1/17]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

◆ SCB_ICSR_VECTPENDING_Pos [2/17]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

◆ SCB_ICSR_VECTPENDING_Pos [3/17]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

◆ SCB_ICSR_VECTPENDING_Pos [4/17]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

◆ SCB_ICSR_VECTPENDING_Pos [5/17]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

◆ SCB_ICSR_VECTPENDING_Pos [6/17]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

◆ SCB_ICSR_VECTPENDING_Pos [7/17]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

◆ SCB_ICSR_VECTPENDING_Pos [8/17]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

◆ SCB_ICSR_VECTPENDING_Pos [9/17]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

◆ SCB_ICSR_VECTPENDING_Pos [10/17]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

◆ SCB_ICSR_VECTPENDING_Pos [11/17]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

◆ SCB_ICSR_VECTPENDING_Pos [12/17]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

◆ SCB_ICSR_VECTPENDING_Pos [13/17]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

◆ SCB_ICSR_VECTPENDING_Pos [14/17]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

◆ SCB_ICSR_VECTPENDING_Pos [15/17]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

◆ SCB_ICSR_VECTPENDING_Pos [16/17]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

◆ SCB_ICSR_VECTPENDING_Pos [17/17]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

◆ SCB_ID_DFR_MProfDbg_Msk [1/3]

#define SCB_ID_DFR_MProfDbg_Msk   (0xFUL << SCB_ID_DFR_MProfDbg_Pos)

SCB ID_DFR: MProfDbg Mask

◆ SCB_ID_DFR_MProfDbg_Msk [2/3]

#define SCB_ID_DFR_MProfDbg_Msk   (0xFUL << SCB_ID_DFR_MProfDbg_Pos)

SCB ID_DFR: MProfDbg Mask

◆ SCB_ID_DFR_MProfDbg_Msk [3/3]

#define SCB_ID_DFR_MProfDbg_Msk   (0xFUL << SCB_ID_DFR_MProfDbg_Pos)

SCB ID_DFR: MProfDbg Mask

◆ SCB_ID_DFR_MProfDbg_Pos [1/3]

#define SCB_ID_DFR_MProfDbg_Pos   20U

SCB ID_DFR: MProfDbg Position

◆ SCB_ID_DFR_MProfDbg_Pos [2/3]

#define SCB_ID_DFR_MProfDbg_Pos   20U

SCB ID_DFR: MProfDbg Position

◆ SCB_ID_DFR_MProfDbg_Pos [3/3]

#define SCB_ID_DFR_MProfDbg_Pos   20U

SCB ID_DFR: MProfDbg Position

◆ SCB_ID_DFR_UDE_Msk [1/3]

#define SCB_ID_DFR_UDE_Msk   (0xFUL << SCB_ID_DFR_UDE_Pos)

SCB ID_DFR: UDE Mask

◆ SCB_ID_DFR_UDE_Msk [2/3]

#define SCB_ID_DFR_UDE_Msk   (0xFUL << SCB_ID_DFR_UDE_Pos)

SCB ID_DFR: UDE Mask

◆ SCB_ID_DFR_UDE_Msk [3/3]

#define SCB_ID_DFR_UDE_Msk   (0xFUL << SCB_ID_DFR_UDE_Pos)

SCB ID_DFR: UDE Mask

◆ SCB_ID_DFR_UDE_Pos [1/3]

#define SCB_ID_DFR_UDE_Pos   28U

SCB ID_DFR: UDE Position

◆ SCB_ID_DFR_UDE_Pos [2/3]

#define SCB_ID_DFR_UDE_Pos   28U

SCB ID_DFR: UDE Position

◆ SCB_ID_DFR_UDE_Pos [3/3]

#define SCB_ID_DFR_UDE_Pos   28U

SCB ID_DFR: UDE Position

◆ SCB_ITCMCR_EN_Msk [1/2]

#define SCB_ITCMCR_EN_Msk   (1UL /*<< SCB_ITCMCR_EN_Pos*/)

SCB ITCMCR: EN Mask

◆ SCB_ITCMCR_EN_Msk [2/2]

#define SCB_ITCMCR_EN_Msk   (1UL /*<< SCB_ITCMCR_EN_Pos*/)

SCB ITCMCR: EN Mask

◆ SCB_ITCMCR_EN_Pos [1/2]

#define SCB_ITCMCR_EN_Pos   0U

SCB ITCMCR: EN Position

◆ SCB_ITCMCR_EN_Pos [2/2]

#define SCB_ITCMCR_EN_Pos   0U

SCB ITCMCR: EN Position

◆ SCB_ITCMCR_RETEN_Msk

#define SCB_ITCMCR_RETEN_Msk   (1UL << SCB_ITCMCR_RETEN_Pos)

SCB ITCMCR: RETEN Mask

◆ SCB_ITCMCR_RETEN_Pos

#define SCB_ITCMCR_RETEN_Pos   2U

SCB ITCMCR: RETEN Position

◆ SCB_ITCMCR_RMW_Msk

#define SCB_ITCMCR_RMW_Msk   (1UL << SCB_ITCMCR_RMW_Pos)

SCB ITCMCR: RMW Mask

◆ SCB_ITCMCR_RMW_Pos

#define SCB_ITCMCR_RMW_Pos   1U

SCB ITCMCR: RMW Position

◆ SCB_ITCMCR_SZ_Msk [1/2]

#define SCB_ITCMCR_SZ_Msk   (0xFUL << SCB_ITCMCR_SZ_Pos)

SCB ITCMCR: SZ Mask

◆ SCB_ITCMCR_SZ_Msk [2/2]

#define SCB_ITCMCR_SZ_Msk   (0xFUL << SCB_ITCMCR_SZ_Pos)

SCB ITCMCR: SZ Mask

◆ SCB_ITCMCR_SZ_Pos [1/2]

#define SCB_ITCMCR_SZ_Pos   3U

SCB ITCMCR: SZ Position

◆ SCB_ITCMCR_SZ_Pos [2/2]

#define SCB_ITCMCR_SZ_Pos   3U

SCB ITCMCR: SZ Position

◆ SCB_NSACR_CP0_Msk [1/3]

#define SCB_NSACR_CP0_Msk   (1UL /*<< SCB_NSACR_CP0_Pos*/)

SCB NSACR: CP0 Mask

◆ SCB_NSACR_CP0_Msk [2/3]

#define SCB_NSACR_CP0_Msk   (1UL /*<< SCB_NSACR_CP0_Pos*/)

SCB NSACR: CP0 Mask

◆ SCB_NSACR_CP0_Msk [3/3]

#define SCB_NSACR_CP0_Msk   (1UL /*<< SCB_NSACR_CP0_Pos*/)

SCB NSACR: CP0 Mask

◆ SCB_NSACR_CP0_Pos [1/3]

#define SCB_NSACR_CP0_Pos   0U

SCB NSACR: CP0 Position

◆ SCB_NSACR_CP0_Pos [2/3]

#define SCB_NSACR_CP0_Pos   0U

SCB NSACR: CP0 Position

◆ SCB_NSACR_CP0_Pos [3/3]

#define SCB_NSACR_CP0_Pos   0U

SCB NSACR: CP0 Position

◆ SCB_NSACR_CP10_Msk [1/7]

#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)

SCB NSACR: CP10 Mask

◆ SCB_NSACR_CP10_Msk [2/7]

#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)

SCB NSACR: CP10 Mask

◆ SCB_NSACR_CP10_Msk [3/7]

#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)

SCB NSACR: CP10 Mask

◆ SCB_NSACR_CP10_Msk [4/7]

#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)

SCB NSACR: CP10 Mask

◆ SCB_NSACR_CP10_Msk [5/7]

#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)

SCB NSACR: CP10 Mask

◆ SCB_NSACR_CP10_Msk [6/7]

#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)

SCB NSACR: CP10 Mask

◆ SCB_NSACR_CP10_Msk [7/7]

#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)

SCB NSACR: CP10 Mask

◆ SCB_NSACR_CP10_Pos [1/7]

#define SCB_NSACR_CP10_Pos   10U

SCB NSACR: CP10 Position

◆ SCB_NSACR_CP10_Pos [2/7]

#define SCB_NSACR_CP10_Pos   10U

SCB NSACR: CP10 Position

◆ SCB_NSACR_CP10_Pos [3/7]

#define SCB_NSACR_CP10_Pos   10U

SCB NSACR: CP10 Position

◆ SCB_NSACR_CP10_Pos [4/7]

#define SCB_NSACR_CP10_Pos   10U

SCB NSACR: CP10 Position

◆ SCB_NSACR_CP10_Pos [5/7]

#define SCB_NSACR_CP10_Pos   10U

SCB NSACR: CP10 Position

◆ SCB_NSACR_CP10_Pos [6/7]

#define SCB_NSACR_CP10_Pos   10U

SCB NSACR: CP10 Position

◆ SCB_NSACR_CP10_Pos [7/7]

#define SCB_NSACR_CP10_Pos   10U

SCB NSACR: CP10 Position

◆ SCB_NSACR_CP11_Msk [1/7]

#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)

SCB NSACR: CP11 Mask

◆ SCB_NSACR_CP11_Msk [2/7]

#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)

SCB NSACR: CP11 Mask

◆ SCB_NSACR_CP11_Msk [3/7]

#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)

SCB NSACR: CP11 Mask

◆ SCB_NSACR_CP11_Msk [4/7]

#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)

SCB NSACR: CP11 Mask

◆ SCB_NSACR_CP11_Msk [5/7]

#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)

SCB NSACR: CP11 Mask

◆ SCB_NSACR_CP11_Msk [6/7]

#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)

SCB NSACR: CP11 Mask

◆ SCB_NSACR_CP11_Msk [7/7]

#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)

SCB NSACR: CP11 Mask

◆ SCB_NSACR_CP11_Pos [1/7]

#define SCB_NSACR_CP11_Pos   11U

SCB NSACR: CP11 Position

◆ SCB_NSACR_CP11_Pos [2/7]

#define SCB_NSACR_CP11_Pos   11U

SCB NSACR: CP11 Position

◆ SCB_NSACR_CP11_Pos [3/7]

#define SCB_NSACR_CP11_Pos   11U

SCB NSACR: CP11 Position

◆ SCB_NSACR_CP11_Pos [4/7]

#define SCB_NSACR_CP11_Pos   11U

SCB NSACR: CP11 Position

◆ SCB_NSACR_CP11_Pos [5/7]

#define SCB_NSACR_CP11_Pos   11U

SCB NSACR: CP11 Position

◆ SCB_NSACR_CP11_Pos [6/7]

#define SCB_NSACR_CP11_Pos   11U

SCB NSACR: CP11 Position

◆ SCB_NSACR_CP11_Pos [7/7]

#define SCB_NSACR_CP11_Pos   11U

SCB NSACR: CP11 Position

◆ SCB_NSACR_CP1_Msk [1/3]

#define SCB_NSACR_CP1_Msk   (1UL << SCB_NSACR_CP1_Pos)

SCB NSACR: CP1 Mask

◆ SCB_NSACR_CP1_Msk [2/3]

#define SCB_NSACR_CP1_Msk   (1UL << SCB_NSACR_CP1_Pos)

SCB NSACR: CP1 Mask

◆ SCB_NSACR_CP1_Msk [3/3]

#define SCB_NSACR_CP1_Msk   (1UL << SCB_NSACR_CP1_Pos)

SCB NSACR: CP1 Mask

◆ SCB_NSACR_CP1_Pos [1/3]

#define SCB_NSACR_CP1_Pos   1U

SCB NSACR: CP1 Position

◆ SCB_NSACR_CP1_Pos [2/3]

#define SCB_NSACR_CP1_Pos   1U

SCB NSACR: CP1 Position

◆ SCB_NSACR_CP1_Pos [3/3]

#define SCB_NSACR_CP1_Pos   1U

SCB NSACR: CP1 Position

◆ SCB_NSACR_CP2_Msk [1/3]

#define SCB_NSACR_CP2_Msk   (1UL << SCB_NSACR_CP2_Pos)

SCB NSACR: CP2 Mask

◆ SCB_NSACR_CP2_Msk [2/3]

#define SCB_NSACR_CP2_Msk   (1UL << SCB_NSACR_CP2_Pos)

SCB NSACR: CP2 Mask

◆ SCB_NSACR_CP2_Msk [3/3]

#define SCB_NSACR_CP2_Msk   (1UL << SCB_NSACR_CP2_Pos)

SCB NSACR: CP2 Mask

◆ SCB_NSACR_CP2_Pos [1/3]

#define SCB_NSACR_CP2_Pos   2U

SCB NSACR: CP2 Position

◆ SCB_NSACR_CP2_Pos [2/3]

#define SCB_NSACR_CP2_Pos   2U

SCB NSACR: CP2 Position

◆ SCB_NSACR_CP2_Pos [3/3]

#define SCB_NSACR_CP2_Pos   2U

SCB NSACR: CP2 Position

◆ SCB_NSACR_CP3_Msk [1/3]

#define SCB_NSACR_CP3_Msk   (1UL << SCB_NSACR_CP3_Pos)

SCB NSACR: CP3 Mask

◆ SCB_NSACR_CP3_Msk [2/3]

#define SCB_NSACR_CP3_Msk   (1UL << SCB_NSACR_CP3_Pos)

SCB NSACR: CP3 Mask

◆ SCB_NSACR_CP3_Msk [3/3]

#define SCB_NSACR_CP3_Msk   (1UL << SCB_NSACR_CP3_Pos)

SCB NSACR: CP3 Mask

◆ SCB_NSACR_CP3_Pos [1/3]

#define SCB_NSACR_CP3_Pos   3U

SCB NSACR: CP3 Position

◆ SCB_NSACR_CP3_Pos [2/3]

#define SCB_NSACR_CP3_Pos   3U

SCB NSACR: CP3 Position

◆ SCB_NSACR_CP3_Pos [3/3]

#define SCB_NSACR_CP3_Pos   3U

SCB NSACR: CP3 Position

◆ SCB_NSACR_CP4_Msk [1/3]

#define SCB_NSACR_CP4_Msk   (1UL << SCB_NSACR_CP4_Pos)

SCB NSACR: CP4 Mask

◆ SCB_NSACR_CP4_Msk [2/3]

#define SCB_NSACR_CP4_Msk   (1UL << SCB_NSACR_CP4_Pos)

SCB NSACR: CP4 Mask

◆ SCB_NSACR_CP4_Msk [3/3]

#define SCB_NSACR_CP4_Msk   (1UL << SCB_NSACR_CP4_Pos)

SCB NSACR: CP4 Mask

◆ SCB_NSACR_CP4_Pos [1/3]

#define SCB_NSACR_CP4_Pos   4U

SCB NSACR: CP4 Position

◆ SCB_NSACR_CP4_Pos [2/3]

#define SCB_NSACR_CP4_Pos   4U

SCB NSACR: CP4 Position

◆ SCB_NSACR_CP4_Pos [3/3]

#define SCB_NSACR_CP4_Pos   4U

SCB NSACR: CP4 Position

◆ SCB_NSACR_CP5_Msk [1/3]

#define SCB_NSACR_CP5_Msk   (1UL << SCB_NSACR_CP5_Pos)

SCB NSACR: CP5 Mask

◆ SCB_NSACR_CP5_Msk [2/3]

#define SCB_NSACR_CP5_Msk   (1UL << SCB_NSACR_CP5_Pos)

SCB NSACR: CP5 Mask

◆ SCB_NSACR_CP5_Msk [3/3]

#define SCB_NSACR_CP5_Msk   (1UL << SCB_NSACR_CP5_Pos)

SCB NSACR: CP5 Mask

◆ SCB_NSACR_CP5_Pos [1/3]

#define SCB_NSACR_CP5_Pos   5U

SCB NSACR: CP5 Position

◆ SCB_NSACR_CP5_Pos [2/3]

#define SCB_NSACR_CP5_Pos   5U

SCB NSACR: CP5 Position

◆ SCB_NSACR_CP5_Pos [3/3]

#define SCB_NSACR_CP5_Pos   5U

SCB NSACR: CP5 Position

◆ SCB_NSACR_CP6_Msk [1/3]

#define SCB_NSACR_CP6_Msk   (1UL << SCB_NSACR_CP6_Pos)

SCB NSACR: CP6 Mask

◆ SCB_NSACR_CP6_Msk [2/3]

#define SCB_NSACR_CP6_Msk   (1UL << SCB_NSACR_CP6_Pos)

SCB NSACR: CP6 Mask

◆ SCB_NSACR_CP6_Msk [3/3]

#define SCB_NSACR_CP6_Msk   (1UL << SCB_NSACR_CP6_Pos)

SCB NSACR: CP6 Mask

◆ SCB_NSACR_CP6_Pos [1/3]

#define SCB_NSACR_CP6_Pos   6U

SCB NSACR: CP6 Position

◆ SCB_NSACR_CP6_Pos [2/3]

#define SCB_NSACR_CP6_Pos   6U

SCB NSACR: CP6 Position

◆ SCB_NSACR_CP6_Pos [3/3]

#define SCB_NSACR_CP6_Pos   6U

SCB NSACR: CP6 Position

◆ SCB_NSACR_CP7_Msk [1/3]

#define SCB_NSACR_CP7_Msk   (1UL << SCB_NSACR_CP7_Pos)

SCB NSACR: CP7 Mask

◆ SCB_NSACR_CP7_Msk [2/3]

#define SCB_NSACR_CP7_Msk   (1UL << SCB_NSACR_CP7_Pos)

SCB NSACR: CP7 Mask

◆ SCB_NSACR_CP7_Msk [3/3]

#define SCB_NSACR_CP7_Msk   (1UL << SCB_NSACR_CP7_Pos)

SCB NSACR: CP7 Mask

◆ SCB_NSACR_CP7_Pos [1/3]

#define SCB_NSACR_CP7_Pos   7U

SCB NSACR: CP7 Position

◆ SCB_NSACR_CP7_Pos [2/3]

#define SCB_NSACR_CP7_Pos   7U

SCB NSACR: CP7 Position

◆ SCB_NSACR_CP7_Pos [3/3]

#define SCB_NSACR_CP7_Pos   7U

SCB NSACR: CP7 Position

◆ SCB_NSACR_CPn_Msk [1/4]

#define SCB_NSACR_CPn_Msk   (1UL /*<< SCB_NSACR_CPn_Pos*/)

SCB NSACR: CPn Mask

◆ SCB_NSACR_CPn_Msk [2/4]

#define SCB_NSACR_CPn_Msk   (1UL /*<< SCB_NSACR_CPn_Pos*/)

SCB NSACR: CPn Mask

◆ SCB_NSACR_CPn_Msk [3/4]

#define SCB_NSACR_CPn_Msk   (1UL /*<< SCB_NSACR_CPn_Pos*/)

SCB NSACR: CPn Mask

◆ SCB_NSACR_CPn_Msk [4/4]

#define SCB_NSACR_CPn_Msk   (1UL /*<< SCB_NSACR_CPn_Pos*/)

SCB NSACR: CPn Mask

◆ SCB_NSACR_CPn_Pos [1/4]

#define SCB_NSACR_CPn_Pos   0U

SCB NSACR: CPn Position

◆ SCB_NSACR_CPn_Pos [2/4]

#define SCB_NSACR_CPn_Pos   0U

SCB NSACR: CPn Position

◆ SCB_NSACR_CPn_Pos [3/4]

#define SCB_NSACR_CPn_Pos   0U

SCB NSACR: CPn Position

◆ SCB_NSACR_CPn_Pos [4/4]

#define SCB_NSACR_CPn_Pos   0U

SCB NSACR: CPn Position

◆ SCB_RFSR_IS_Msk [1/3]

#define SCB_RFSR_IS_Msk   (0x7FFFUL << SCB_RFSR_IS_Pos)

SCB RFSR: IS Mask

◆ SCB_RFSR_IS_Msk [2/3]

#define SCB_RFSR_IS_Msk   (0x7FFFUL << SCB_RFSR_IS_Pos)

SCB RFSR: IS Mask

◆ SCB_RFSR_IS_Msk [3/3]

#define SCB_RFSR_IS_Msk   (0x7FFFUL << SCB_RFSR_IS_Pos)

SCB RFSR: IS Mask

◆ SCB_RFSR_IS_Pos [1/3]

#define SCB_RFSR_IS_Pos   16U

SCB RFSR: IS Position

◆ SCB_RFSR_IS_Pos [2/3]

#define SCB_RFSR_IS_Pos   16U

SCB RFSR: IS Position

◆ SCB_RFSR_IS_Pos [3/3]

#define SCB_RFSR_IS_Pos   16U

SCB RFSR: IS Position

◆ SCB_RFSR_UET_Msk [1/3]

#define SCB_RFSR_UET_Msk   (3UL /*<< SCB_RFSR_UET_Pos*/)

SCB RFSR: UET Mask

◆ SCB_RFSR_UET_Msk [2/3]

#define SCB_RFSR_UET_Msk   (3UL /*<< SCB_RFSR_UET_Pos*/)

SCB RFSR: UET Mask

◆ SCB_RFSR_UET_Msk [3/3]

#define SCB_RFSR_UET_Msk   (3UL /*<< SCB_RFSR_UET_Pos*/)

SCB RFSR: UET Mask

◆ SCB_RFSR_UET_Pos [1/3]

#define SCB_RFSR_UET_Pos   0U

SCB RFSR: UET Position

◆ SCB_RFSR_UET_Pos [2/3]

#define SCB_RFSR_UET_Pos   0U

SCB RFSR: UET Position

◆ SCB_RFSR_UET_Pos [3/3]

#define SCB_RFSR_UET_Pos   0U

SCB RFSR: UET Position

◆ SCB_RFSR_V_Msk [1/3]

#define SCB_RFSR_V_Msk   (1UL << SCB_RFSR_V_Pos)

SCB RFSR: V Mask

◆ SCB_RFSR_V_Msk [2/3]

#define SCB_RFSR_V_Msk   (1UL << SCB_RFSR_V_Pos)

SCB RFSR: V Mask

◆ SCB_RFSR_V_Msk [3/3]

#define SCB_RFSR_V_Msk   (1UL << SCB_RFSR_V_Pos)

SCB RFSR: V Mask

◆ SCB_RFSR_V_Pos [1/3]

#define SCB_RFSR_V_Pos   31U

SCB RFSR: V Position

◆ SCB_RFSR_V_Pos [2/3]

#define SCB_RFSR_V_Pos   31U

SCB RFSR: V Position

◆ SCB_RFSR_V_Pos [3/3]

#define SCB_RFSR_V_Pos   31U

SCB RFSR: V Position

◆ SCB_SCR_SEVONPEND_Msk [1/17]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

◆ SCB_SCR_SEVONPEND_Msk [2/17]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

◆ SCB_SCR_SEVONPEND_Msk [3/17]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

◆ SCB_SCR_SEVONPEND_Msk [4/17]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

◆ SCB_SCR_SEVONPEND_Msk [5/17]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

◆ SCB_SCR_SEVONPEND_Msk [6/17]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

◆ SCB_SCR_SEVONPEND_Msk [7/17]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

◆ SCB_SCR_SEVONPEND_Msk [8/17]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

◆ SCB_SCR_SEVONPEND_Msk [9/17]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

◆ SCB_SCR_SEVONPEND_Msk [10/17]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

◆ SCB_SCR_SEVONPEND_Msk [11/17]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

◆ SCB_SCR_SEVONPEND_Msk [12/17]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

◆ SCB_SCR_SEVONPEND_Msk [13/17]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

◆ SCB_SCR_SEVONPEND_Msk [14/17]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

◆ SCB_SCR_SEVONPEND_Msk [15/17]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

◆ SCB_SCR_SEVONPEND_Msk [16/17]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

◆ SCB_SCR_SEVONPEND_Msk [17/17]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

◆ SCB_SCR_SEVONPEND_Pos [1/17]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

◆ SCB_SCR_SEVONPEND_Pos [2/17]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

◆ SCB_SCR_SEVONPEND_Pos [3/17]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

◆ SCB_SCR_SEVONPEND_Pos [4/17]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

◆ SCB_SCR_SEVONPEND_Pos [5/17]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

◆ SCB_SCR_SEVONPEND_Pos [6/17]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

◆ SCB_SCR_SEVONPEND_Pos [7/17]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

◆ SCB_SCR_SEVONPEND_Pos [8/17]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

◆ SCB_SCR_SEVONPEND_Pos [9/17]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

◆ SCB_SCR_SEVONPEND_Pos [10/17]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

◆ SCB_SCR_SEVONPEND_Pos [11/17]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

◆ SCB_SCR_SEVONPEND_Pos [12/17]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

◆ SCB_SCR_SEVONPEND_Pos [13/17]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

◆ SCB_SCR_SEVONPEND_Pos [14/17]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

◆ SCB_SCR_SEVONPEND_Pos [15/17]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

◆ SCB_SCR_SEVONPEND_Pos [16/17]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

◆ SCB_SCR_SEVONPEND_Pos [17/17]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

◆ SCB_SCR_SLEEPDEEP_Msk [1/17]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

◆ SCB_SCR_SLEEPDEEP_Msk [2/17]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

◆ SCB_SCR_SLEEPDEEP_Msk [3/17]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

◆ SCB_SCR_SLEEPDEEP_Msk [4/17]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

◆ SCB_SCR_SLEEPDEEP_Msk [5/17]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

◆ SCB_SCR_SLEEPDEEP_Msk [6/17]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

◆ SCB_SCR_SLEEPDEEP_Msk [7/17]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

◆ SCB_SCR_SLEEPDEEP_Msk [8/17]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

◆ SCB_SCR_SLEEPDEEP_Msk [9/17]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

◆ SCB_SCR_SLEEPDEEP_Msk [10/17]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

◆ SCB_SCR_SLEEPDEEP_Msk [11/17]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

◆ SCB_SCR_SLEEPDEEP_Msk [12/17]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

◆ SCB_SCR_SLEEPDEEP_Msk [13/17]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

◆ SCB_SCR_SLEEPDEEP_Msk [14/17]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

◆ SCB_SCR_SLEEPDEEP_Msk [15/17]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

◆ SCB_SCR_SLEEPDEEP_Msk [16/17]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

◆ SCB_SCR_SLEEPDEEP_Msk [17/17]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

◆ SCB_SCR_SLEEPDEEP_Pos [1/17]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

◆ SCB_SCR_SLEEPDEEP_Pos [2/17]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

◆ SCB_SCR_SLEEPDEEP_Pos [3/17]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

◆ SCB_SCR_SLEEPDEEP_Pos [4/17]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

◆ SCB_SCR_SLEEPDEEP_Pos [5/17]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

◆ SCB_SCR_SLEEPDEEP_Pos [6/17]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

◆ SCB_SCR_SLEEPDEEP_Pos [7/17]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

◆ SCB_SCR_SLEEPDEEP_Pos [8/17]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

◆ SCB_SCR_SLEEPDEEP_Pos [9/17]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

◆ SCB_SCR_SLEEPDEEP_Pos [10/17]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

◆ SCB_SCR_SLEEPDEEP_Pos [11/17]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

◆ SCB_SCR_SLEEPDEEP_Pos [12/17]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

◆ SCB_SCR_SLEEPDEEP_Pos [13/17]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

◆ SCB_SCR_SLEEPDEEP_Pos [14/17]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

◆ SCB_SCR_SLEEPDEEP_Pos [15/17]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

◆ SCB_SCR_SLEEPDEEP_Pos [16/17]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

◆ SCB_SCR_SLEEPDEEP_Pos [17/17]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

◆ SCB_SCR_SLEEPDEEPS_Msk [1/9]

#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

◆ SCB_SCR_SLEEPDEEPS_Msk [2/9]

#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

◆ SCB_SCR_SLEEPDEEPS_Msk [3/9]

#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

◆ SCB_SCR_SLEEPDEEPS_Msk [4/9]

#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

◆ SCB_SCR_SLEEPDEEPS_Msk [5/9]

#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

◆ SCB_SCR_SLEEPDEEPS_Msk [6/9]

#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

◆ SCB_SCR_SLEEPDEEPS_Msk [7/9]

#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

◆ SCB_SCR_SLEEPDEEPS_Msk [8/9]

#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

◆ SCB_SCR_SLEEPDEEPS_Msk [9/9]

#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

◆ SCB_SCR_SLEEPDEEPS_Pos [1/9]

#define SCB_SCR_SLEEPDEEPS_Pos   3U

SCB SCR: SLEEPDEEPS Position

◆ SCB_SCR_SLEEPDEEPS_Pos [2/9]

#define SCB_SCR_SLEEPDEEPS_Pos   3U

SCB SCR: SLEEPDEEPS Position

◆ SCB_SCR_SLEEPDEEPS_Pos [3/9]

#define SCB_SCR_SLEEPDEEPS_Pos   3U

SCB SCR: SLEEPDEEPS Position

◆ SCB_SCR_SLEEPDEEPS_Pos [4/9]

#define SCB_SCR_SLEEPDEEPS_Pos   3U

SCB SCR: SLEEPDEEPS Position

◆ SCB_SCR_SLEEPDEEPS_Pos [5/9]

#define SCB_SCR_SLEEPDEEPS_Pos   3U

SCB SCR: SLEEPDEEPS Position

◆ SCB_SCR_SLEEPDEEPS_Pos [6/9]

#define SCB_SCR_SLEEPDEEPS_Pos   3U

SCB SCR: SLEEPDEEPS Position

◆ SCB_SCR_SLEEPDEEPS_Pos [7/9]

#define SCB_SCR_SLEEPDEEPS_Pos   3U

SCB SCR: SLEEPDEEPS Position

◆ SCB_SCR_SLEEPDEEPS_Pos [8/9]

#define SCB_SCR_SLEEPDEEPS_Pos   3U

SCB SCR: SLEEPDEEPS Position

◆ SCB_SCR_SLEEPDEEPS_Pos [9/9]

#define SCB_SCR_SLEEPDEEPS_Pos   3U

SCB SCR: SLEEPDEEPS Position

◆ SCB_SCR_SLEEPONEXIT_Msk [1/17]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

◆ SCB_SCR_SLEEPONEXIT_Msk [2/17]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

◆ SCB_SCR_SLEEPONEXIT_Msk [3/17]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

◆ SCB_SCR_SLEEPONEXIT_Msk [4/17]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

◆ SCB_SCR_SLEEPONEXIT_Msk [5/17]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

◆ SCB_SCR_SLEEPONEXIT_Msk [6/17]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

◆ SCB_SCR_SLEEPONEXIT_Msk [7/17]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

◆ SCB_SCR_SLEEPONEXIT_Msk [8/17]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

◆ SCB_SCR_SLEEPONEXIT_Msk [9/17]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

◆ SCB_SCR_SLEEPONEXIT_Msk [10/17]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

◆ SCB_SCR_SLEEPONEXIT_Msk [11/17]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

◆ SCB_SCR_SLEEPONEXIT_Msk [12/17]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

◆ SCB_SCR_SLEEPONEXIT_Msk [13/17]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

◆ SCB_SCR_SLEEPONEXIT_Msk [14/17]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

◆ SCB_SCR_SLEEPONEXIT_Msk [15/17]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

◆ SCB_SCR_SLEEPONEXIT_Msk [16/17]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

◆ SCB_SCR_SLEEPONEXIT_Msk [17/17]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

◆ SCB_SCR_SLEEPONEXIT_Pos [1/17]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

◆ SCB_SCR_SLEEPONEXIT_Pos [2/17]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

◆ SCB_SCR_SLEEPONEXIT_Pos [3/17]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

◆ SCB_SCR_SLEEPONEXIT_Pos [4/17]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

◆ SCB_SCR_SLEEPONEXIT_Pos [5/17]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

◆ SCB_SCR_SLEEPONEXIT_Pos [6/17]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

◆ SCB_SCR_SLEEPONEXIT_Pos [7/17]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

◆ SCB_SCR_SLEEPONEXIT_Pos [8/17]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

◆ SCB_SCR_SLEEPONEXIT_Pos [9/17]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

◆ SCB_SCR_SLEEPONEXIT_Pos [10/17]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

◆ SCB_SCR_SLEEPONEXIT_Pos [11/17]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

◆ SCB_SCR_SLEEPONEXIT_Pos [12/17]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

◆ SCB_SCR_SLEEPONEXIT_Pos [13/17]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

◆ SCB_SCR_SLEEPONEXIT_Pos [14/17]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

◆ SCB_SCR_SLEEPONEXIT_Pos [15/17]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

◆ SCB_SCR_SLEEPONEXIT_Pos [16/17]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

◆ SCB_SCR_SLEEPONEXIT_Pos [17/17]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

◆ SCB_SHCSR_BUSFAULTACT_Msk [1/11]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

◆ SCB_SHCSR_BUSFAULTACT_Msk [2/11]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

◆ SCB_SHCSR_BUSFAULTACT_Msk [3/11]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

◆ SCB_SHCSR_BUSFAULTACT_Msk [4/11]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

◆ SCB_SHCSR_BUSFAULTACT_Msk [5/11]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

◆ SCB_SHCSR_BUSFAULTACT_Msk [6/11]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

◆ SCB_SHCSR_BUSFAULTACT_Msk [7/11]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

◆ SCB_SHCSR_BUSFAULTACT_Msk [8/11]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

◆ SCB_SHCSR_BUSFAULTACT_Msk [9/11]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

◆ SCB_SHCSR_BUSFAULTACT_Msk [10/11]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

◆ SCB_SHCSR_BUSFAULTACT_Msk [11/11]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

◆ SCB_SHCSR_BUSFAULTACT_Pos [1/11]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

◆ SCB_SHCSR_BUSFAULTACT_Pos [2/11]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

◆ SCB_SHCSR_BUSFAULTACT_Pos [3/11]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

◆ SCB_SHCSR_BUSFAULTACT_Pos [4/11]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

◆ SCB_SHCSR_BUSFAULTACT_Pos [5/11]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

◆ SCB_SHCSR_BUSFAULTACT_Pos [6/11]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

◆ SCB_SHCSR_BUSFAULTACT_Pos [7/11]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

◆ SCB_SHCSR_BUSFAULTACT_Pos [8/11]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

◆ SCB_SHCSR_BUSFAULTACT_Pos [9/11]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

◆ SCB_SHCSR_BUSFAULTACT_Pos [10/11]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

◆ SCB_SHCSR_BUSFAULTACT_Pos [11/11]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

◆ SCB_SHCSR_BUSFAULTENA_Msk [1/11]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

◆ SCB_SHCSR_BUSFAULTENA_Msk [2/11]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

◆ SCB_SHCSR_BUSFAULTENA_Msk [3/11]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

◆ SCB_SHCSR_BUSFAULTENA_Msk [4/11]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

◆ SCB_SHCSR_BUSFAULTENA_Msk [5/11]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

◆ SCB_SHCSR_BUSFAULTENA_Msk [6/11]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

◆ SCB_SHCSR_BUSFAULTENA_Msk [7/11]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

◆ SCB_SHCSR_BUSFAULTENA_Msk [8/11]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

◆ SCB_SHCSR_BUSFAULTENA_Msk [9/11]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

◆ SCB_SHCSR_BUSFAULTENA_Msk [10/11]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

◆ SCB_SHCSR_BUSFAULTENA_Msk [11/11]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

◆ SCB_SHCSR_BUSFAULTENA_Pos [1/11]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

◆ SCB_SHCSR_BUSFAULTENA_Pos [2/11]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

◆ SCB_SHCSR_BUSFAULTENA_Pos [3/11]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

◆ SCB_SHCSR_BUSFAULTENA_Pos [4/11]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

◆ SCB_SHCSR_BUSFAULTENA_Pos [5/11]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

◆ SCB_SHCSR_BUSFAULTENA_Pos [6/11]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

◆ SCB_SHCSR_BUSFAULTENA_Pos [7/11]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

◆ SCB_SHCSR_BUSFAULTENA_Pos [8/11]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

◆ SCB_SHCSR_BUSFAULTENA_Pos [9/11]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

◆ SCB_SHCSR_BUSFAULTENA_Pos [10/11]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

◆ SCB_SHCSR_BUSFAULTENA_Pos [11/11]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [1/11]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [2/11]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [3/11]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [4/11]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [5/11]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [6/11]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [7/11]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [8/11]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [9/11]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [10/11]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [11/11]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [1/11]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [2/11]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [3/11]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [4/11]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [5/11]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [6/11]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [7/11]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [8/11]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [9/11]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [10/11]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [11/11]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

◆ SCB_SHCSR_HARDFAULTACT_Msk [1/9]

#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

◆ SCB_SHCSR_HARDFAULTACT_Msk [2/9]

#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

◆ SCB_SHCSR_HARDFAULTACT_Msk [3/9]

#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

◆ SCB_SHCSR_HARDFAULTACT_Msk [4/9]

#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

◆ SCB_SHCSR_HARDFAULTACT_Msk [5/9]

#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

◆ SCB_SHCSR_HARDFAULTACT_Msk [6/9]

#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

◆ SCB_SHCSR_HARDFAULTACT_Msk [7/9]

#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

◆ SCB_SHCSR_HARDFAULTACT_Msk [8/9]

#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

◆ SCB_SHCSR_HARDFAULTACT_Msk [9/9]

#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

◆ SCB_SHCSR_HARDFAULTACT_Pos [1/9]

#define SCB_SHCSR_HARDFAULTACT_Pos   2U

SCB SHCSR: HARDFAULTACT Position

◆ SCB_SHCSR_HARDFAULTACT_Pos [2/9]

#define SCB_SHCSR_HARDFAULTACT_Pos   2U

SCB SHCSR: HARDFAULTACT Position

◆ SCB_SHCSR_HARDFAULTACT_Pos [3/9]

#define SCB_SHCSR_HARDFAULTACT_Pos   2U

SCB SHCSR: HARDFAULTACT Position

◆ SCB_SHCSR_HARDFAULTACT_Pos [4/9]

#define SCB_SHCSR_HARDFAULTACT_Pos   2U

SCB SHCSR: HARDFAULTACT Position

◆ SCB_SHCSR_HARDFAULTACT_Pos [5/9]

#define SCB_SHCSR_HARDFAULTACT_Pos   2U

SCB SHCSR: HARDFAULTACT Position

◆ SCB_SHCSR_HARDFAULTACT_Pos [6/9]

#define SCB_SHCSR_HARDFAULTACT_Pos   2U

SCB SHCSR: HARDFAULTACT Position

◆ SCB_SHCSR_HARDFAULTACT_Pos [7/9]

#define SCB_SHCSR_HARDFAULTACT_Pos   2U

SCB SHCSR: HARDFAULTACT Position

◆ SCB_SHCSR_HARDFAULTACT_Pos [8/9]

#define SCB_SHCSR_HARDFAULTACT_Pos   2U

SCB SHCSR: HARDFAULTACT Position

◆ SCB_SHCSR_HARDFAULTACT_Pos [9/9]

#define SCB_SHCSR_HARDFAULTACT_Pos   2U

SCB SHCSR: HARDFAULTACT Position

◆ SCB_SHCSR_HARDFAULTPENDED_Msk [1/9]

#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

◆ SCB_SHCSR_HARDFAULTPENDED_Msk [2/9]

#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

◆ SCB_SHCSR_HARDFAULTPENDED_Msk [3/9]

#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

◆ SCB_SHCSR_HARDFAULTPENDED_Msk [4/9]

#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

◆ SCB_SHCSR_HARDFAULTPENDED_Msk [5/9]

#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

◆ SCB_SHCSR_HARDFAULTPENDED_Msk [6/9]

#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

◆ SCB_SHCSR_HARDFAULTPENDED_Msk [7/9]

#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

◆ SCB_SHCSR_HARDFAULTPENDED_Msk [8/9]

#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

◆ SCB_SHCSR_HARDFAULTPENDED_Msk [9/9]

#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

◆ SCB_SHCSR_HARDFAULTPENDED_Pos [1/9]

#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U

SCB SHCSR: HARDFAULTPENDED Position

◆ SCB_SHCSR_HARDFAULTPENDED_Pos [2/9]

#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U

SCB SHCSR: HARDFAULTPENDED Position

◆ SCB_SHCSR_HARDFAULTPENDED_Pos [3/9]

#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U

SCB SHCSR: HARDFAULTPENDED Position

◆ SCB_SHCSR_HARDFAULTPENDED_Pos [4/9]

#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U

SCB SHCSR: HARDFAULTPENDED Position

◆ SCB_SHCSR_HARDFAULTPENDED_Pos [5/9]

#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U

SCB SHCSR: HARDFAULTPENDED Position

◆ SCB_SHCSR_HARDFAULTPENDED_Pos [6/9]

#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U

SCB SHCSR: HARDFAULTPENDED Position

◆ SCB_SHCSR_HARDFAULTPENDED_Pos [7/9]

#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U

SCB SHCSR: HARDFAULTPENDED Position

◆ SCB_SHCSR_HARDFAULTPENDED_Pos [8/9]

#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U

SCB SHCSR: HARDFAULTPENDED Position

◆ SCB_SHCSR_HARDFAULTPENDED_Pos [9/9]

#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U

SCB SHCSR: HARDFAULTPENDED Position

◆ SCB_SHCSR_MEMFAULTACT_Msk [1/11]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

◆ SCB_SHCSR_MEMFAULTACT_Msk [2/11]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

◆ SCB_SHCSR_MEMFAULTACT_Msk [3/11]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

◆ SCB_SHCSR_MEMFAULTACT_Msk [4/11]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

◆ SCB_SHCSR_MEMFAULTACT_Msk [5/11]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

◆ SCB_SHCSR_MEMFAULTACT_Msk [6/11]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

◆ SCB_SHCSR_MEMFAULTACT_Msk [7/11]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

◆ SCB_SHCSR_MEMFAULTACT_Msk [8/11]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

◆ SCB_SHCSR_MEMFAULTACT_Msk [9/11]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

◆ SCB_SHCSR_MEMFAULTACT_Msk [10/11]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

◆ SCB_SHCSR_MEMFAULTACT_Msk [11/11]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

◆ SCB_SHCSR_MEMFAULTACT_Pos [1/11]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

◆ SCB_SHCSR_MEMFAULTACT_Pos [2/11]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

◆ SCB_SHCSR_MEMFAULTACT_Pos [3/11]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

◆ SCB_SHCSR_MEMFAULTACT_Pos [4/11]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

◆ SCB_SHCSR_MEMFAULTACT_Pos [5/11]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

◆ SCB_SHCSR_MEMFAULTACT_Pos [6/11]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

◆ SCB_SHCSR_MEMFAULTACT_Pos [7/11]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

◆ SCB_SHCSR_MEMFAULTACT_Pos [8/11]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

◆ SCB_SHCSR_MEMFAULTACT_Pos [9/11]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

◆ SCB_SHCSR_MEMFAULTACT_Pos [10/11]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

◆ SCB_SHCSR_MEMFAULTACT_Pos [11/11]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

◆ SCB_SHCSR_MEMFAULTENA_Msk [1/11]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

◆ SCB_SHCSR_MEMFAULTENA_Msk [2/11]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

◆ SCB_SHCSR_MEMFAULTENA_Msk [3/11]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

◆ SCB_SHCSR_MEMFAULTENA_Msk [4/11]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

◆ SCB_SHCSR_MEMFAULTENA_Msk [5/11]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

◆ SCB_SHCSR_MEMFAULTENA_Msk [6/11]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

◆ SCB_SHCSR_MEMFAULTENA_Msk [7/11]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

◆ SCB_SHCSR_MEMFAULTENA_Msk [8/11]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

◆ SCB_SHCSR_MEMFAULTENA_Msk [9/11]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

◆ SCB_SHCSR_MEMFAULTENA_Msk [10/11]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

◆ SCB_SHCSR_MEMFAULTENA_Msk [11/11]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

◆ SCB_SHCSR_MEMFAULTENA_Pos [1/11]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

◆ SCB_SHCSR_MEMFAULTENA_Pos [2/11]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

◆ SCB_SHCSR_MEMFAULTENA_Pos [3/11]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

◆ SCB_SHCSR_MEMFAULTENA_Pos [4/11]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

◆ SCB_SHCSR_MEMFAULTENA_Pos [5/11]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

◆ SCB_SHCSR_MEMFAULTENA_Pos [6/11]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

◆ SCB_SHCSR_MEMFAULTENA_Pos [7/11]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

◆ SCB_SHCSR_MEMFAULTENA_Pos [8/11]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

◆ SCB_SHCSR_MEMFAULTENA_Pos [9/11]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

◆ SCB_SHCSR_MEMFAULTENA_Pos [10/11]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

◆ SCB_SHCSR_MEMFAULTENA_Pos [11/11]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [1/11]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [2/11]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [3/11]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [4/11]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [5/11]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [6/11]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [7/11]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [8/11]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [9/11]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [10/11]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [11/11]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [1/11]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [2/11]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [3/11]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [4/11]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [5/11]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [6/11]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [7/11]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [8/11]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [9/11]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [10/11]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [11/11]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

◆ SCB_SHCSR_MONITORACT_Msk [1/11]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

◆ SCB_SHCSR_MONITORACT_Msk [2/11]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

◆ SCB_SHCSR_MONITORACT_Msk [3/11]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

◆ SCB_SHCSR_MONITORACT_Msk [4/11]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

◆ SCB_SHCSR_MONITORACT_Msk [5/11]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

◆ SCB_SHCSR_MONITORACT_Msk [6/11]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

◆ SCB_SHCSR_MONITORACT_Msk [7/11]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

◆ SCB_SHCSR_MONITORACT_Msk [8/11]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

◆ SCB_SHCSR_MONITORACT_Msk [9/11]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

◆ SCB_SHCSR_MONITORACT_Msk [10/11]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

◆ SCB_SHCSR_MONITORACT_Msk [11/11]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

◆ SCB_SHCSR_MONITORACT_Pos [1/11]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

◆ SCB_SHCSR_MONITORACT_Pos [2/11]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

◆ SCB_SHCSR_MONITORACT_Pos [3/11]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

◆ SCB_SHCSR_MONITORACT_Pos [4/11]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

◆ SCB_SHCSR_MONITORACT_Pos [5/11]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

◆ SCB_SHCSR_MONITORACT_Pos [6/11]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

◆ SCB_SHCSR_MONITORACT_Pos [7/11]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

◆ SCB_SHCSR_MONITORACT_Pos [8/11]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

◆ SCB_SHCSR_MONITORACT_Pos [9/11]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

◆ SCB_SHCSR_MONITORACT_Pos [10/11]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

◆ SCB_SHCSR_MONITORACT_Pos [11/11]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

◆ SCB_SHCSR_NMIACT_Msk [1/9]

#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

◆ SCB_SHCSR_NMIACT_Msk [2/9]

#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

◆ SCB_SHCSR_NMIACT_Msk [3/9]

#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

◆ SCB_SHCSR_NMIACT_Msk [4/9]

#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

◆ SCB_SHCSR_NMIACT_Msk [5/9]

#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

◆ SCB_SHCSR_NMIACT_Msk [6/9]

#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

◆ SCB_SHCSR_NMIACT_Msk [7/9]

#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

◆ SCB_SHCSR_NMIACT_Msk [8/9]

#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

◆ SCB_SHCSR_NMIACT_Msk [9/9]

#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

◆ SCB_SHCSR_NMIACT_Pos [1/9]

#define SCB_SHCSR_NMIACT_Pos   5U

SCB SHCSR: NMIACT Position

◆ SCB_SHCSR_NMIACT_Pos [2/9]

#define SCB_SHCSR_NMIACT_Pos   5U

SCB SHCSR: NMIACT Position

◆ SCB_SHCSR_NMIACT_Pos [3/9]

#define SCB_SHCSR_NMIACT_Pos   5U

SCB SHCSR: NMIACT Position

◆ SCB_SHCSR_NMIACT_Pos [4/9]

#define SCB_SHCSR_NMIACT_Pos   5U

SCB SHCSR: NMIACT Position

◆ SCB_SHCSR_NMIACT_Pos [5/9]

#define SCB_SHCSR_NMIACT_Pos   5U

SCB SHCSR: NMIACT Position

◆ SCB_SHCSR_NMIACT_Pos [6/9]

#define SCB_SHCSR_NMIACT_Pos   5U

SCB SHCSR: NMIACT Position

◆ SCB_SHCSR_NMIACT_Pos [7/9]

#define SCB_SHCSR_NMIACT_Pos   5U

SCB SHCSR: NMIACT Position

◆ SCB_SHCSR_NMIACT_Pos [8/9]

#define SCB_SHCSR_NMIACT_Pos   5U

SCB SHCSR: NMIACT Position

◆ SCB_SHCSR_NMIACT_Pos [9/9]

#define SCB_SHCSR_NMIACT_Pos   5U

SCB SHCSR: NMIACT Position

◆ SCB_SHCSR_PENDSVACT_Msk [1/13]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

◆ SCB_SHCSR_PENDSVACT_Msk [2/13]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

◆ SCB_SHCSR_PENDSVACT_Msk [3/13]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

◆ SCB_SHCSR_PENDSVACT_Msk [4/13]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

◆ SCB_SHCSR_PENDSVACT_Msk [5/13]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

◆ SCB_SHCSR_PENDSVACT_Msk [6/13]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

◆ SCB_SHCSR_PENDSVACT_Msk [7/13]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

◆ SCB_SHCSR_PENDSVACT_Msk [8/13]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

◆ SCB_SHCSR_PENDSVACT_Msk [9/13]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

◆ SCB_SHCSR_PENDSVACT_Msk [10/13]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

◆ SCB_SHCSR_PENDSVACT_Msk [11/13]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

◆ SCB_SHCSR_PENDSVACT_Msk [12/13]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

◆ SCB_SHCSR_PENDSVACT_Msk [13/13]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

◆ SCB_SHCSR_PENDSVACT_Pos [1/13]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

◆ SCB_SHCSR_PENDSVACT_Pos [2/13]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

◆ SCB_SHCSR_PENDSVACT_Pos [3/13]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

◆ SCB_SHCSR_PENDSVACT_Pos [4/13]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

◆ SCB_SHCSR_PENDSVACT_Pos [5/13]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

◆ SCB_SHCSR_PENDSVACT_Pos [6/13]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

◆ SCB_SHCSR_PENDSVACT_Pos [7/13]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

◆ SCB_SHCSR_PENDSVACT_Pos [8/13]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

◆ SCB_SHCSR_PENDSVACT_Pos [9/13]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

◆ SCB_SHCSR_PENDSVACT_Pos [10/13]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

◆ SCB_SHCSR_PENDSVACT_Pos [11/13]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

◆ SCB_SHCSR_PENDSVACT_Pos [12/13]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

◆ SCB_SHCSR_PENDSVACT_Pos [13/13]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

◆ SCB_SHCSR_SECUREFAULTACT_Msk [1/7]

#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)

SCB SHCSR: SECUREFAULTACT Mask

◆ SCB_SHCSR_SECUREFAULTACT_Msk [2/7]

#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)

SCB SHCSR: SECUREFAULTACT Mask

◆ SCB_SHCSR_SECUREFAULTACT_Msk [3/7]

#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)

SCB SHCSR: SECUREFAULTACT Mask

◆ SCB_SHCSR_SECUREFAULTACT_Msk [4/7]

#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)

SCB SHCSR: SECUREFAULTACT Mask

◆ SCB_SHCSR_SECUREFAULTACT_Msk [5/7]

#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)

SCB SHCSR: SECUREFAULTACT Mask

◆ SCB_SHCSR_SECUREFAULTACT_Msk [6/7]

#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)

SCB SHCSR: SECUREFAULTACT Mask

◆ SCB_SHCSR_SECUREFAULTACT_Msk [7/7]

#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)

SCB SHCSR: SECUREFAULTACT Mask

◆ SCB_SHCSR_SECUREFAULTACT_Pos [1/7]

#define SCB_SHCSR_SECUREFAULTACT_Pos   4U

SCB SHCSR: SECUREFAULTACT Position

◆ SCB_SHCSR_SECUREFAULTACT_Pos [2/7]

#define SCB_SHCSR_SECUREFAULTACT_Pos   4U

SCB SHCSR: SECUREFAULTACT Position

◆ SCB_SHCSR_SECUREFAULTACT_Pos [3/7]

#define SCB_SHCSR_SECUREFAULTACT_Pos   4U

SCB SHCSR: SECUREFAULTACT Position

◆ SCB_SHCSR_SECUREFAULTACT_Pos [4/7]

#define SCB_SHCSR_SECUREFAULTACT_Pos   4U

SCB SHCSR: SECUREFAULTACT Position

◆ SCB_SHCSR_SECUREFAULTACT_Pos [5/7]

#define SCB_SHCSR_SECUREFAULTACT_Pos   4U

SCB SHCSR: SECUREFAULTACT Position

◆ SCB_SHCSR_SECUREFAULTACT_Pos [6/7]

#define SCB_SHCSR_SECUREFAULTACT_Pos   4U

SCB SHCSR: SECUREFAULTACT Position

◆ SCB_SHCSR_SECUREFAULTACT_Pos [7/7]

#define SCB_SHCSR_SECUREFAULTACT_Pos   4U

SCB SHCSR: SECUREFAULTACT Position

◆ SCB_SHCSR_SECUREFAULTENA_Msk [1/7]

#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)

SCB SHCSR: SECUREFAULTENA Mask

◆ SCB_SHCSR_SECUREFAULTENA_Msk [2/7]

#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)

SCB SHCSR: SECUREFAULTENA Mask

◆ SCB_SHCSR_SECUREFAULTENA_Msk [3/7]

#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)

SCB SHCSR: SECUREFAULTENA Mask

◆ SCB_SHCSR_SECUREFAULTENA_Msk [4/7]

#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)

SCB SHCSR: SECUREFAULTENA Mask

◆ SCB_SHCSR_SECUREFAULTENA_Msk [5/7]

#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)

SCB SHCSR: SECUREFAULTENA Mask

◆ SCB_SHCSR_SECUREFAULTENA_Msk [6/7]

#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)

SCB SHCSR: SECUREFAULTENA Mask

◆ SCB_SHCSR_SECUREFAULTENA_Msk [7/7]

#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)

SCB SHCSR: SECUREFAULTENA Mask

◆ SCB_SHCSR_SECUREFAULTENA_Pos [1/7]

#define SCB_SHCSR_SECUREFAULTENA_Pos   19U

SCB SHCSR: SECUREFAULTENA Position

◆ SCB_SHCSR_SECUREFAULTENA_Pos [2/7]

#define SCB_SHCSR_SECUREFAULTENA_Pos   19U

SCB SHCSR: SECUREFAULTENA Position

◆ SCB_SHCSR_SECUREFAULTENA_Pos [3/7]

#define SCB_SHCSR_SECUREFAULTENA_Pos   19U

SCB SHCSR: SECUREFAULTENA Position

◆ SCB_SHCSR_SECUREFAULTENA_Pos [4/7]

#define SCB_SHCSR_SECUREFAULTENA_Pos   19U

SCB SHCSR: SECUREFAULTENA Position

◆ SCB_SHCSR_SECUREFAULTENA_Pos [5/7]

#define SCB_SHCSR_SECUREFAULTENA_Pos   19U

SCB SHCSR: SECUREFAULTENA Position

◆ SCB_SHCSR_SECUREFAULTENA_Pos [6/7]

#define SCB_SHCSR_SECUREFAULTENA_Pos   19U

SCB SHCSR: SECUREFAULTENA Position

◆ SCB_SHCSR_SECUREFAULTENA_Pos [7/7]

#define SCB_SHCSR_SECUREFAULTENA_Pos   19U

SCB SHCSR: SECUREFAULTENA Position

◆ SCB_SHCSR_SECUREFAULTPENDED_Msk [1/7]

#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)

SCB SHCSR: SECUREFAULTPENDED Mask

◆ SCB_SHCSR_SECUREFAULTPENDED_Msk [2/7]

#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)

SCB SHCSR: SECUREFAULTPENDED Mask

◆ SCB_SHCSR_SECUREFAULTPENDED_Msk [3/7]

#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)

SCB SHCSR: SECUREFAULTPENDED Mask

◆ SCB_SHCSR_SECUREFAULTPENDED_Msk [4/7]

#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)

SCB SHCSR: SECUREFAULTPENDED Mask

◆ SCB_SHCSR_SECUREFAULTPENDED_Msk [5/7]

#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)

SCB SHCSR: SECUREFAULTPENDED Mask

◆ SCB_SHCSR_SECUREFAULTPENDED_Msk [6/7]

#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)

SCB SHCSR: SECUREFAULTPENDED Mask

◆ SCB_SHCSR_SECUREFAULTPENDED_Msk [7/7]

#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)

SCB SHCSR: SECUREFAULTPENDED Mask

◆ SCB_SHCSR_SECUREFAULTPENDED_Pos [1/7]

#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U

SCB SHCSR: SECUREFAULTPENDED Position

◆ SCB_SHCSR_SECUREFAULTPENDED_Pos [2/7]

#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U

SCB SHCSR: SECUREFAULTPENDED Position

◆ SCB_SHCSR_SECUREFAULTPENDED_Pos [3/7]

#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U

SCB SHCSR: SECUREFAULTPENDED Position

◆ SCB_SHCSR_SECUREFAULTPENDED_Pos [4/7]

#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U

SCB SHCSR: SECUREFAULTPENDED Position

◆ SCB_SHCSR_SECUREFAULTPENDED_Pos [5/7]

#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U

SCB SHCSR: SECUREFAULTPENDED Position

◆ SCB_SHCSR_SECUREFAULTPENDED_Pos [6/7]

#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U

SCB SHCSR: SECUREFAULTPENDED Position

◆ SCB_SHCSR_SECUREFAULTPENDED_Pos [7/7]

#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U

SCB SHCSR: SECUREFAULTPENDED Position

◆ SCB_SHCSR_SVCALLACT_Msk [1/13]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

◆ SCB_SHCSR_SVCALLACT_Msk [2/13]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

◆ SCB_SHCSR_SVCALLACT_Msk [3/13]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

◆ SCB_SHCSR_SVCALLACT_Msk [4/13]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

◆ SCB_SHCSR_SVCALLACT_Msk [5/13]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

◆ SCB_SHCSR_SVCALLACT_Msk [6/13]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

◆ SCB_SHCSR_SVCALLACT_Msk [7/13]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

◆ SCB_SHCSR_SVCALLACT_Msk [8/13]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

◆ SCB_SHCSR_SVCALLACT_Msk [9/13]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

◆ SCB_SHCSR_SVCALLACT_Msk [10/13]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

◆ SCB_SHCSR_SVCALLACT_Msk [11/13]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

◆ SCB_SHCSR_SVCALLACT_Msk [12/13]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

◆ SCB_SHCSR_SVCALLACT_Msk [13/13]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

◆ SCB_SHCSR_SVCALLACT_Pos [1/13]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

◆ SCB_SHCSR_SVCALLACT_Pos [2/13]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

◆ SCB_SHCSR_SVCALLACT_Pos [3/13]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

◆ SCB_SHCSR_SVCALLACT_Pos [4/13]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

◆ SCB_SHCSR_SVCALLACT_Pos [5/13]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

◆ SCB_SHCSR_SVCALLACT_Pos [6/13]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

◆ SCB_SHCSR_SVCALLACT_Pos [7/13]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

◆ SCB_SHCSR_SVCALLACT_Pos [8/13]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

◆ SCB_SHCSR_SVCALLACT_Pos [9/13]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

◆ SCB_SHCSR_SVCALLACT_Pos [10/13]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

◆ SCB_SHCSR_SVCALLACT_Pos [11/13]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

◆ SCB_SHCSR_SVCALLACT_Pos [12/13]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

◆ SCB_SHCSR_SVCALLACT_Pos [13/13]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

◆ SCB_SHCSR_SVCALLPENDED_Msk [1/17]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

◆ SCB_SHCSR_SVCALLPENDED_Msk [2/17]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

◆ SCB_SHCSR_SVCALLPENDED_Msk [3/17]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

◆ SCB_SHCSR_SVCALLPENDED_Msk [4/17]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

◆ SCB_SHCSR_SVCALLPENDED_Msk [5/17]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

◆ SCB_SHCSR_SVCALLPENDED_Msk [6/17]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

◆ SCB_SHCSR_SVCALLPENDED_Msk [7/17]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

◆ SCB_SHCSR_SVCALLPENDED_Msk [8/17]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

◆ SCB_SHCSR_SVCALLPENDED_Msk [9/17]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

◆ SCB_SHCSR_SVCALLPENDED_Msk [10/17]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

◆ SCB_SHCSR_SVCALLPENDED_Msk [11/17]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

◆ SCB_SHCSR_SVCALLPENDED_Msk [12/17]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

◆ SCB_SHCSR_SVCALLPENDED_Msk [13/17]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

◆ SCB_SHCSR_SVCALLPENDED_Msk [14/17]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

◆ SCB_SHCSR_SVCALLPENDED_Msk [15/17]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

◆ SCB_SHCSR_SVCALLPENDED_Msk [16/17]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

◆ SCB_SHCSR_SVCALLPENDED_Msk [17/17]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

◆ SCB_SHCSR_SVCALLPENDED_Pos [1/17]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

◆ SCB_SHCSR_SVCALLPENDED_Pos [2/17]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

◆ SCB_SHCSR_SVCALLPENDED_Pos [3/17]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

◆ SCB_SHCSR_SVCALLPENDED_Pos [4/17]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

◆ SCB_SHCSR_SVCALLPENDED_Pos [5/17]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

◆ SCB_SHCSR_SVCALLPENDED_Pos [6/17]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

◆ SCB_SHCSR_SVCALLPENDED_Pos [7/17]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

◆ SCB_SHCSR_SVCALLPENDED_Pos [8/17]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

◆ SCB_SHCSR_SVCALLPENDED_Pos [9/17]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

◆ SCB_SHCSR_SVCALLPENDED_Pos [10/17]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

◆ SCB_SHCSR_SVCALLPENDED_Pos [11/17]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

◆ SCB_SHCSR_SVCALLPENDED_Pos [12/17]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

◆ SCB_SHCSR_SVCALLPENDED_Pos [13/17]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

◆ SCB_SHCSR_SVCALLPENDED_Pos [14/17]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

◆ SCB_SHCSR_SVCALLPENDED_Pos [15/17]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

◆ SCB_SHCSR_SVCALLPENDED_Pos [16/17]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

◆ SCB_SHCSR_SVCALLPENDED_Pos [17/17]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

◆ SCB_SHCSR_SYSTICKACT_Msk [1/13]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

◆ SCB_SHCSR_SYSTICKACT_Msk [2/13]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

◆ SCB_SHCSR_SYSTICKACT_Msk [3/13]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

◆ SCB_SHCSR_SYSTICKACT_Msk [4/13]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

◆ SCB_SHCSR_SYSTICKACT_Msk [5/13]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

◆ SCB_SHCSR_SYSTICKACT_Msk [6/13]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

◆ SCB_SHCSR_SYSTICKACT_Msk [7/13]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

◆ SCB_SHCSR_SYSTICKACT_Msk [8/13]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

◆ SCB_SHCSR_SYSTICKACT_Msk [9/13]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

◆ SCB_SHCSR_SYSTICKACT_Msk [10/13]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

◆ SCB_SHCSR_SYSTICKACT_Msk [11/13]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

◆ SCB_SHCSR_SYSTICKACT_Msk [12/13]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

◆ SCB_SHCSR_SYSTICKACT_Msk [13/13]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

◆ SCB_SHCSR_SYSTICKACT_Pos [1/13]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

◆ SCB_SHCSR_SYSTICKACT_Pos [2/13]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

◆ SCB_SHCSR_SYSTICKACT_Pos [3/13]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

◆ SCB_SHCSR_SYSTICKACT_Pos [4/13]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

◆ SCB_SHCSR_SYSTICKACT_Pos [5/13]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

◆ SCB_SHCSR_SYSTICKACT_Pos [6/13]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

◆ SCB_SHCSR_SYSTICKACT_Pos [7/13]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

◆ SCB_SHCSR_SYSTICKACT_Pos [8/13]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

◆ SCB_SHCSR_SYSTICKACT_Pos [9/13]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

◆ SCB_SHCSR_SYSTICKACT_Pos [10/13]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

◆ SCB_SHCSR_SYSTICKACT_Pos [11/13]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

◆ SCB_SHCSR_SYSTICKACT_Pos [12/13]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

◆ SCB_SHCSR_SYSTICKACT_Pos [13/13]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

◆ SCB_SHCSR_USGFAULTACT_Msk [1/11]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

◆ SCB_SHCSR_USGFAULTACT_Msk [2/11]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

◆ SCB_SHCSR_USGFAULTACT_Msk [3/11]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

◆ SCB_SHCSR_USGFAULTACT_Msk [4/11]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

◆ SCB_SHCSR_USGFAULTACT_Msk [5/11]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

◆ SCB_SHCSR_USGFAULTACT_Msk [6/11]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

◆ SCB_SHCSR_USGFAULTACT_Msk [7/11]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

◆ SCB_SHCSR_USGFAULTACT_Msk [8/11]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

◆ SCB_SHCSR_USGFAULTACT_Msk [9/11]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

◆ SCB_SHCSR_USGFAULTACT_Msk [10/11]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

◆ SCB_SHCSR_USGFAULTACT_Msk [11/11]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

◆ SCB_SHCSR_USGFAULTACT_Pos [1/11]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

◆ SCB_SHCSR_USGFAULTACT_Pos [2/11]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

◆ SCB_SHCSR_USGFAULTACT_Pos [3/11]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

◆ SCB_SHCSR_USGFAULTACT_Pos [4/11]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

◆ SCB_SHCSR_USGFAULTACT_Pos [5/11]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

◆ SCB_SHCSR_USGFAULTACT_Pos [6/11]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

◆ SCB_SHCSR_USGFAULTACT_Pos [7/11]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

◆ SCB_SHCSR_USGFAULTACT_Pos [8/11]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

◆ SCB_SHCSR_USGFAULTACT_Pos [9/11]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

◆ SCB_SHCSR_USGFAULTACT_Pos [10/11]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

◆ SCB_SHCSR_USGFAULTACT_Pos [11/11]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

◆ SCB_SHCSR_USGFAULTENA_Msk [1/11]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

◆ SCB_SHCSR_USGFAULTENA_Msk [2/11]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

◆ SCB_SHCSR_USGFAULTENA_Msk [3/11]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

◆ SCB_SHCSR_USGFAULTENA_Msk [4/11]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

◆ SCB_SHCSR_USGFAULTENA_Msk [5/11]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

◆ SCB_SHCSR_USGFAULTENA_Msk [6/11]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

◆ SCB_SHCSR_USGFAULTENA_Msk [7/11]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

◆ SCB_SHCSR_USGFAULTENA_Msk [8/11]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

◆ SCB_SHCSR_USGFAULTENA_Msk [9/11]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

◆ SCB_SHCSR_USGFAULTENA_Msk [10/11]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

◆ SCB_SHCSR_USGFAULTENA_Msk [11/11]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

◆ SCB_SHCSR_USGFAULTENA_Pos [1/11]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

◆ SCB_SHCSR_USGFAULTENA_Pos [2/11]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

◆ SCB_SHCSR_USGFAULTENA_Pos [3/11]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

◆ SCB_SHCSR_USGFAULTENA_Pos [4/11]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

◆ SCB_SHCSR_USGFAULTENA_Pos [5/11]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

◆ SCB_SHCSR_USGFAULTENA_Pos [6/11]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

◆ SCB_SHCSR_USGFAULTENA_Pos [7/11]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

◆ SCB_SHCSR_USGFAULTENA_Pos [8/11]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

◆ SCB_SHCSR_USGFAULTENA_Pos [9/11]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

◆ SCB_SHCSR_USGFAULTENA_Pos [10/11]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

◆ SCB_SHCSR_USGFAULTENA_Pos [11/11]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

◆ SCB_SHCSR_USGFAULTPENDED_Msk [1/11]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

◆ SCB_SHCSR_USGFAULTPENDED_Msk [2/11]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

◆ SCB_SHCSR_USGFAULTPENDED_Msk [3/11]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

◆ SCB_SHCSR_USGFAULTPENDED_Msk [4/11]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

◆ SCB_SHCSR_USGFAULTPENDED_Msk [5/11]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

◆ SCB_SHCSR_USGFAULTPENDED_Msk [6/11]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

◆ SCB_SHCSR_USGFAULTPENDED_Msk [7/11]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

◆ SCB_SHCSR_USGFAULTPENDED_Msk [8/11]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

◆ SCB_SHCSR_USGFAULTPENDED_Msk [9/11]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

◆ SCB_SHCSR_USGFAULTPENDED_Msk [10/11]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

◆ SCB_SHCSR_USGFAULTPENDED_Msk [11/11]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

◆ SCB_SHCSR_USGFAULTPENDED_Pos [1/11]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

◆ SCB_SHCSR_USGFAULTPENDED_Pos [2/11]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

◆ SCB_SHCSR_USGFAULTPENDED_Pos [3/11]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

◆ SCB_SHCSR_USGFAULTPENDED_Pos [4/11]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

◆ SCB_SHCSR_USGFAULTPENDED_Pos [5/11]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

◆ SCB_SHCSR_USGFAULTPENDED_Pos [6/11]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

◆ SCB_SHCSR_USGFAULTPENDED_Pos [7/11]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

◆ SCB_SHCSR_USGFAULTPENDED_Pos [8/11]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

◆ SCB_SHCSR_USGFAULTPENDED_Pos [9/11]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

◆ SCB_SHCSR_USGFAULTPENDED_Pos [10/11]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

◆ SCB_SHCSR_USGFAULTPENDED_Pos [11/11]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

◆ SCB_STIR_INTID_Msk [1/8]

#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

◆ SCB_STIR_INTID_Msk [2/8]

#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

◆ SCB_STIR_INTID_Msk [3/8]

#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

◆ SCB_STIR_INTID_Msk [4/8]

#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

◆ SCB_STIR_INTID_Msk [5/8]

#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

◆ SCB_STIR_INTID_Msk [6/8]

#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

◆ SCB_STIR_INTID_Msk [7/8]

#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

◆ SCB_STIR_INTID_Msk [8/8]

#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

◆ SCB_STIR_INTID_Pos [1/8]

#define SCB_STIR_INTID_Pos   0U

SCB STIR: INTID Position

◆ SCB_STIR_INTID_Pos [2/8]

#define SCB_STIR_INTID_Pos   0U

SCB STIR: INTID Position

◆ SCB_STIR_INTID_Pos [3/8]

#define SCB_STIR_INTID_Pos   0U

SCB STIR: INTID Position

◆ SCB_STIR_INTID_Pos [4/8]

#define SCB_STIR_INTID_Pos   0U

SCB STIR: INTID Position

◆ SCB_STIR_INTID_Pos [5/8]

#define SCB_STIR_INTID_Pos   0U

SCB STIR: INTID Position

◆ SCB_STIR_INTID_Pos [6/8]

#define SCB_STIR_INTID_Pos   0U

SCB STIR: INTID Position

◆ SCB_STIR_INTID_Pos [7/8]

#define SCB_STIR_INTID_Pos   0U

SCB STIR: INTID Position

◆ SCB_STIR_INTID_Pos [8/8]

#define SCB_STIR_INTID_Pos   0U

SCB STIR: INTID Position

◆ SCB_VTOR_TBLBASE_Msk

#define SCB_VTOR_TBLBASE_Msk   (1UL << SCB_VTOR_TBLBASE_Pos)

SCB VTOR: TBLBASE Mask

◆ SCB_VTOR_TBLBASE_Pos

#define SCB_VTOR_TBLBASE_Pos   29U

SCB VTOR: TBLBASE Position

◆ SCB_VTOR_TBLOFF_Msk [1/12]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

◆ SCB_VTOR_TBLOFF_Msk [2/12]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

◆ SCB_VTOR_TBLOFF_Msk [3/12]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

◆ SCB_VTOR_TBLOFF_Msk [4/12]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

◆ SCB_VTOR_TBLOFF_Msk [5/12]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

◆ SCB_VTOR_TBLOFF_Msk [6/12]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

◆ SCB_VTOR_TBLOFF_Msk [7/12]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

◆ SCB_VTOR_TBLOFF_Msk [8/12]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

◆ SCB_VTOR_TBLOFF_Msk [9/12]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

◆ SCB_VTOR_TBLOFF_Msk [10/12]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

◆ SCB_VTOR_TBLOFF_Msk [11/12]

#define SCB_VTOR_TBLOFF_Msk   (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

◆ SCB_VTOR_TBLOFF_Msk [12/12]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

◆ SCB_VTOR_TBLOFF_Pos [1/12]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

◆ SCB_VTOR_TBLOFF_Pos [2/12]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

◆ SCB_VTOR_TBLOFF_Pos [3/12]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

◆ SCB_VTOR_TBLOFF_Pos [4/12]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

◆ SCB_VTOR_TBLOFF_Pos [5/12]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

◆ SCB_VTOR_TBLOFF_Pos [6/12]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

◆ SCB_VTOR_TBLOFF_Pos [7/12]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

◆ SCB_VTOR_TBLOFF_Pos [8/12]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

◆ SCB_VTOR_TBLOFF_Pos [9/12]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

◆ SCB_VTOR_TBLOFF_Pos [10/12]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

◆ SCB_VTOR_TBLOFF_Pos [11/12]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

◆ SCB_VTOR_TBLOFF_Pos [12/12]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

◆ SCnSCB_ACTLR_DISMCYCINT_Msk

#define SCnSCB_ACTLR_DISMCYCINT_Msk   (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)

ACTLR: DISMCYCINT Mask

◆ SCnSCB_ACTLR_DISMCYCINT_Pos

#define SCnSCB_ACTLR_DISMCYCINT_Pos   0U

ACTLR: DISMCYCINT Position

◆ TPI_ACPR_SWOSCALER_Msk [1/5]

#define TPI_ACPR_SWOSCALER_Msk   (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)

TPI ACPR: SWOSCALER Mask

◆ TPI_ACPR_SWOSCALER_Msk [2/5]

#define TPI_ACPR_SWOSCALER_Msk   (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)

TPI ACPR: SWOSCALER Mask

◆ TPI_ACPR_SWOSCALER_Msk [3/5]

#define TPI_ACPR_SWOSCALER_Msk   (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)

TPI ACPR: SWOSCALER Mask

◆ TPI_ACPR_SWOSCALER_Msk [4/5]

#define TPI_ACPR_SWOSCALER_Msk   (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)

TPI ACPR: SWOSCALER Mask

◆ TPI_ACPR_SWOSCALER_Msk [5/5]

#define TPI_ACPR_SWOSCALER_Msk   (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)

TPI ACPR: SWOSCALER Mask

◆ TPI_ACPR_SWOSCALER_Pos [1/5]

#define TPI_ACPR_SWOSCALER_Pos   0U

TPI ACPR: SWOSCALER Position

◆ TPI_ACPR_SWOSCALER_Pos [2/5]

#define TPI_ACPR_SWOSCALER_Pos   0U

TPI ACPR: SWOSCALER Position

◆ TPI_ACPR_SWOSCALER_Pos [3/5]

#define TPI_ACPR_SWOSCALER_Pos   0U

TPI ACPR: SWOSCALER Position

◆ TPI_ACPR_SWOSCALER_Pos [4/5]

#define TPI_ACPR_SWOSCALER_Pos   0U

TPI ACPR: SWOSCALER Position

◆ TPI_ACPR_SWOSCALER_Pos [5/5]

#define TPI_ACPR_SWOSCALER_Pos   0U

TPI ACPR: SWOSCALER Position

◆ TPI_FFCR_EnFmt_Msk [1/3]

#define TPI_FFCR_EnFmt_Msk   (0x3UL << /*TPI_FFCR_EnFmt_Pos*/)

TPI FFCR: EnFmt Mask

◆ TPI_FFCR_EnFmt_Msk [2/3]

#define TPI_FFCR_EnFmt_Msk   (0x3UL << /*TPI_FFCR_EnFmt_Pos*/)

TPI FFCR: EnFmt Mask

◆ TPI_FFCR_EnFmt_Msk [3/3]

#define TPI_FFCR_EnFmt_Msk   (0x3UL << /*TPI_FFCR_EnFmt_Pos*/)

TPI FFCR: EnFmt Mask

◆ TPI_FFCR_EnFmt_Pos [1/3]

#define TPI_FFCR_EnFmt_Pos   0U

TPI FFCR: EnFmt Position

◆ TPI_FFCR_EnFmt_Pos [2/3]

#define TPI_FFCR_EnFmt_Pos   0U

TPI FFCR: EnFmt Position

◆ TPI_FFCR_EnFmt_Pos [3/3]

#define TPI_FFCR_EnFmt_Pos   0U

TPI FFCR: EnFmt Position

◆ TPI_LSR_nTT_Msk [1/5]

#define TPI_LSR_nTT_Msk   (0x1UL << TPI_LSR_nTT_Pos)

TPI LSR: Not thirty-two bit. Mask

◆ TPI_LSR_nTT_Msk [2/5]

#define TPI_LSR_nTT_Msk   (0x1UL << TPI_LSR_nTT_Pos)

TPI LSR: Not thirty-two bit. Mask

◆ TPI_LSR_nTT_Msk [3/5]

#define TPI_LSR_nTT_Msk   (0x1UL << TPI_LSR_nTT_Pos)

TPI LSR: Not thirty-two bit. Mask

◆ TPI_LSR_nTT_Msk [4/5]

#define TPI_LSR_nTT_Msk   (0x1UL << TPI_LSR_nTT_Pos)

TPI LSR: Not thirty-two bit. Mask

◆ TPI_LSR_nTT_Msk [5/5]

#define TPI_LSR_nTT_Msk   (0x1UL << TPI_LSR_nTT_Pos)

TPI LSR: Not thirty-two bit. Mask

◆ TPI_LSR_nTT_Pos [1/5]

#define TPI_LSR_nTT_Pos   1U

TPI LSR: Not thirty-two bit. Position

◆ TPI_LSR_nTT_Pos [2/5]

#define TPI_LSR_nTT_Pos   1U

TPI LSR: Not thirty-two bit. Position

◆ TPI_LSR_nTT_Pos [3/5]

#define TPI_LSR_nTT_Pos   1U

TPI LSR: Not thirty-two bit. Position

◆ TPI_LSR_nTT_Pos [4/5]

#define TPI_LSR_nTT_Pos   1U

TPI LSR: Not thirty-two bit. Position

◆ TPI_LSR_nTT_Pos [5/5]

#define TPI_LSR_nTT_Pos   1U

TPI LSR: Not thirty-two bit. Position

◆ TPI_LSR_SLI_Msk [1/5]

#define TPI_LSR_SLI_Msk   (0x1UL /*<< TPI_LSR_SLI_Pos*/)

TPI LSR: Software Lock implemented Mask

◆ TPI_LSR_SLI_Msk [2/5]

#define TPI_LSR_SLI_Msk   (0x1UL /*<< TPI_LSR_SLI_Pos*/)

TPI LSR: Software Lock implemented Mask

◆ TPI_LSR_SLI_Msk [3/5]

#define TPI_LSR_SLI_Msk   (0x1UL /*<< TPI_LSR_SLI_Pos*/)

TPI LSR: Software Lock implemented Mask

◆ TPI_LSR_SLI_Msk [4/5]

#define TPI_LSR_SLI_Msk   (0x1UL /*<< TPI_LSR_SLI_Pos*/)

TPI LSR: Software Lock implemented Mask

◆ TPI_LSR_SLI_Msk [5/5]

#define TPI_LSR_SLI_Msk   (0x1UL /*<< TPI_LSR_SLI_Pos*/)

TPI LSR: Software Lock implemented Mask

◆ TPI_LSR_SLI_Pos [1/5]

#define TPI_LSR_SLI_Pos   0U

TPI LSR: Software Lock implemented Position

◆ TPI_LSR_SLI_Pos [2/5]

#define TPI_LSR_SLI_Pos   0U

TPI LSR: Software Lock implemented Position

◆ TPI_LSR_SLI_Pos [3/5]

#define TPI_LSR_SLI_Pos   0U

TPI LSR: Software Lock implemented Position

◆ TPI_LSR_SLI_Pos [4/5]

#define TPI_LSR_SLI_Pos   0U

TPI LSR: Software Lock implemented Position

◆ TPI_LSR_SLI_Pos [5/5]

#define TPI_LSR_SLI_Pos   0U

TPI LSR: Software Lock implemented Position

◆ TPI_LSR_SLK_Msk [1/5]

#define TPI_LSR_SLK_Msk   (0x1UL << TPI_LSR_SLK_Pos)

TPI LSR: Software Lock status Mask

◆ TPI_LSR_SLK_Msk [2/5]

#define TPI_LSR_SLK_Msk   (0x1UL << TPI_LSR_SLK_Pos)

TPI LSR: Software Lock status Mask

◆ TPI_LSR_SLK_Msk [3/5]

#define TPI_LSR_SLK_Msk   (0x1UL << TPI_LSR_SLK_Pos)

TPI LSR: Software Lock status Mask

◆ TPI_LSR_SLK_Msk [4/5]

#define TPI_LSR_SLK_Msk   (0x1UL << TPI_LSR_SLK_Pos)

TPI LSR: Software Lock status Mask

◆ TPI_LSR_SLK_Msk [5/5]

#define TPI_LSR_SLK_Msk   (0x1UL << TPI_LSR_SLK_Pos)

TPI LSR: Software Lock status Mask

◆ TPI_LSR_SLK_Pos [1/5]

#define TPI_LSR_SLK_Pos   1U

TPI LSR: Software Lock status Position

◆ TPI_LSR_SLK_Pos [2/5]

#define TPI_LSR_SLK_Pos   1U

TPI LSR: Software Lock status Position

◆ TPI_LSR_SLK_Pos [3/5]

#define TPI_LSR_SLK_Pos   1U

TPI LSR: Software Lock status Position

◆ TPI_LSR_SLK_Pos [4/5]

#define TPI_LSR_SLK_Pos   1U

TPI LSR: Software Lock status Position

◆ TPI_LSR_SLK_Pos [5/5]

#define TPI_LSR_SLK_Pos   1U

TPI LSR: Software Lock status Position

◆ TPI_PSCR_PSCount_Msk [1/5]

#define TPI_PSCR_PSCount_Msk   (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)

TPI PSCR: TPSCount Mask

◆ TPI_PSCR_PSCount_Msk [2/5]

#define TPI_PSCR_PSCount_Msk   (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)

TPI PSCR: TPSCount Mask

◆ TPI_PSCR_PSCount_Msk [3/5]

#define TPI_PSCR_PSCount_Msk   (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)

TPI PSCR: TPSCount Mask

◆ TPI_PSCR_PSCount_Msk [4/5]

#define TPI_PSCR_PSCount_Msk   (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)

TPI PSCR: TPSCount Mask

◆ TPI_PSCR_PSCount_Msk [5/5]

#define TPI_PSCR_PSCount_Msk   (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)

TPI PSCR: TPSCount Mask

◆ TPI_PSCR_PSCount_Pos [1/5]

#define TPI_PSCR_PSCount_Pos   0U

TPI PSCR: PSCount Position

◆ TPI_PSCR_PSCount_Pos [2/5]

#define TPI_PSCR_PSCount_Pos   0U

TPI PSCR: PSCount Position

◆ TPI_PSCR_PSCount_Pos [3/5]

#define TPI_PSCR_PSCount_Pos   0U

TPI PSCR: PSCount Position

◆ TPI_PSCR_PSCount_Pos [4/5]

#define TPI_PSCR_PSCount_Pos   0U

TPI PSCR: PSCount Position

◆ TPI_PSCR_PSCount_Pos [5/5]

#define TPI_PSCR_PSCount_Pos   0U

TPI PSCR: PSCount Position

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